公开(公告)号：US20180130656A1

公开(公告)日：2018-05-10

申请号：US15843649

申请日：2017-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson Robert Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James Mcardle ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09349864B1

公开(公告)日：2016-05-24

申请号：US14826477

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Timothy James Mcardle ,  Judson Robert Holt ,  Churamani Gaire

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2254 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: Methods for fabricating integrated circuits including selectively forming layers of increased dopant concentration are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a material layer with a selected facet on a selected plane and a non-selected facet on a non-selected plane. The method further includes performing an epitaxial deposition process with a dopant source to grow an in-situ doped epitaxial material on the material layer. The epitaxial deposition process grows the in-situ doped epitaxial material on the selected facet at a first growth rate and over the non-selected facet at a second growth rate greater than the first growth rate. A layer of increased dopant concentration is selectively formed over the selected facet.

Abstract translation: 提供了包括选择性地形成增加的掺杂剂浓度的层的集成电路的制造方法。 在一个实施例中，用于制造集成电路的方法包括在未选择的平面上在所选择的平面上形成具有选定面的材料层和未选择的面。 该方法还包括用掺杂剂源执行外延沉积工艺以在材料层上生长原位掺杂的外延材料。 外延沉积工艺以选择的小平面上的原位掺杂外延材料以第一生长速率和非选择的平面以大于第一生长速率的第二生长速率生长。 在选定的刻面上选择性地形成增加掺杂剂浓度的层。