公开(公告)号：US09147696B2

公开(公告)日：2015-09-29

申请号：US14043243

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Andy Wei ,  Lun Zhao ,  Dae Geun Yang ,  Jin Ping Liu ,  Tien-Ying Luo ,  Guillaume Bouche ,  Mariappan Hariharaputhiran ,  Churamani Gaire

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

公开(公告)号：US09882052B2

公开(公告)日：2018-01-30

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James McArdle ,  Murat Kerem Akarvardar

IPC: H01L21/335 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09349864B1

公开(公告)日：2016-05-24

申请号：US14826477

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Timothy James Mcardle ,  Judson Robert Holt ,  Churamani Gaire

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2254 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: Methods for fabricating integrated circuits including selectively forming layers of increased dopant concentration are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a material layer with a selected facet on a selected plane and a non-selected facet on a non-selected plane. The method further includes performing an epitaxial deposition process with a dopant source to grow an in-situ doped epitaxial material on the material layer. The epitaxial deposition process grows the in-situ doped epitaxial material on the selected facet at a first growth rate and over the non-selected facet at a second growth rate greater than the first growth rate. A layer of increased dopant concentration is selectively formed over the selected facet.

Abstract translation: 提供了包括选择性地形成增加的掺杂剂浓度的层的集成电路的制造方法。 在一个实施例中，用于制造集成电路的方法包括在未选择的平面上在所选择的平面上形成具有选定面的材料层和未选择的面。 该方法还包括用掺杂剂源执行外延沉积工艺以在材料层上生长原位掺杂的外延材料。 外延沉积工艺以选择的小平面上的原位掺杂外延材料以第一生长速率和非选择的平面以大于第一生长速率的第二生长速率生长。 在选定的刻面上选择性地形成增加掺杂剂浓度的层。

公开(公告)号：US20180130656A1

公开(公告)日：2018-05-10

申请号：US15843649

申请日：2017-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson Robert Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James Mcardle ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US20150214345A1

公开(公告)日：2015-07-30

申请号：US14164368

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jinping Liu ,  Churamani Gaire ,  Mariappan Hariharaputhiran ,  Andy Chih-Hung Wei ,  Bharat V. Krishnan ,  Cuiqin Xu ,  Michael Ganz

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/88 ,  H01L29/73 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66151 ,  H01L29/0653 ,  H01L29/1004 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7311 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/88

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.

Abstract translation: 提供了用于在集成电路（IC）器件（例如，金属氧化物半导体场效应晶体管（MOSFET））中隔离源极和漏极区域的方法。 具体地，该器件包括形成在衬底上的栅极结构，与栅极结构相邻嵌入在衬底内的源极和漏极（S / D）以及S / D和衬底之间的衬里层（例如，硅 - 碳） 。 在一种方法中，衬垫层也形成在S / D的顶部。 因此，形成在接合部中的衬垫层防止掺杂剂从源极/漏极扩散。