公开(公告)号：US20180261457A1

公开(公告)日：2018-09-13

申请号：US15457200

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Errol Todd Ryan ,  Nicholas LiCausi

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US08815685B2

公开(公告)日：2014-08-26

申请号：US13755246

申请日：2013-01-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicholas LiCausi ,  Jody Fronheiser ,  Errol Todd Ryan

IPC: H01L21/336 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3105 ,  H01L29/66795

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof. An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的方法。 根据一个实施例，该方法包括形成至少部分地由限制隔离材料界定的半导体衬底的一部分。 衬垫电介质覆盖在限制隔离材料上，并被处理以钝化其表面。 然后将半导体材料的外延层生长在半导体衬底的一部分上。

公开(公告)号：US20140213037A1

公开(公告)日：2014-07-31

申请号：US13755246

申请日：2013-01-31

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Nicholas LiCausi ,  Jody Fronheiser ,  Errol Todd Ryan

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3105 ,  H01L29/66795

Abstract: Methods are provided for fabricating integrated circuits. In accordance with one embodiment, the method includes forming a portion of a semiconductor substrate at least partially bounded by a confinement isolation material. A liner dielectric is formed overlying the confinement isolation material and is treated to passivate a surface thereof An epitaxial layer of semiconductor material is then grown overlying the portion of semiconductor substrate.

Abstract translation: 提供了用于制造集成电路的方法。 根据一个实施例，该方法包括形成至少部分地由限制隔离材料界定的半导体衬底的一部分。 形成衬垫电介质覆盖在限制隔离材料上，并被处理以钝化其表面。然后，半导体材料的外延层生长在半导体衬底的该部分上。

公开(公告)号：US10211100B2

公开(公告)日：2019-02-19

申请号：US15469701

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

IPC: H01L21/764 ,  H01L21/768

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.

公开(公告)号：US10163633B2

公开(公告)日：2018-12-25

申请号：US15457200

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Errol Todd Ryan ,  Nicholas LiCausi

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US20180277430A1

公开(公告)日：2018-09-27

申请号：US15469701

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Andre Labonte ,  Nicholas LiCausi ,  Guillaume Bouche ,  Chanro Park

IPC: H01L21/768 ,  H01L21/764

CPC classification number: H01L21/76879 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/7685

Abstract: One method includes performing an etching process to define a gate cavity that exposes an upper surface and at least a portion of the sidewalls of a gate structure and forming a replacement spacer structure adjacent the exposed sidewalls of the gate structure, wherein the replacement spacer structure exposes a portion of the upper surface of the gate structure and includes at least one air space. In this example, the method also includes forming a conformal etch stop layer and a replacement gate cap structure in the gate cavity, selectively removing a portion of the replacement gate cap structure and a portion of the conformal etch stop layer so as to thereby expose the upper surface of the gate structure, and forming a conductive gate contact structure (CB) in the conductive gate contact opening, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region.