公开(公告)号：US09466547B1

公开(公告)日：2016-10-11

申请号：US14734600

申请日：2015-06-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/54

CPC classification number: H01L23/3171 ,  H01L21/4853 ,  H01L21/563 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/03

Abstract: A topographical structure is formed within an integrated circuit (IC) chip passivation layer. The topographical structure includes a trench extending below the top surface of the passivation layer and above the top surface of an uppermost inter-metallic dielectric layer underlying the passivation layer associated with the uppermost wiring line of the IC chip. The topographical structure may also include a ridge above the top surface of the passivation layer along the perimeter of the trench. The topographical structure may be positioned between a series of IC chip contact pads and/or may be positioned around a particular IC chip contact pad. The topographical structures increase the surface area of the passivation layer resulting in increased underfill bonding to the passivation layer. The topographical structures also influence capillary movement of capillary underfill and may be positioned to speed up, slow down, or divert the movement of the capillary underfill.

Abstract translation: 在集成电路（IC）芯片钝化层内形成一种形貌结构。 形貌结构包括在钝化层的顶表面下方延伸的沟槽，并且在与IC芯片的最上面布线相关联的钝化层下面的最上面的金属间介电层的顶表面之上。 形貌结构还可以包括沿着沟槽的周边的钝化层的顶表面上方的脊。 形状结构可以位于一系列IC芯片接触焊盘之间和/或可以位于特定的IC芯片接触焊盘周围。 形貌结构增加了钝化层的表面积，从而增加了与钝化层的底部填充结合。 地形结构还影响毛细管底部填充物的毛细管运动，并且可以定位成加速，减慢或转移毛细管底部填充物的移动。

公开(公告)号：US09343420B2

公开(公告)日：2016-05-17

申请号：US14181616

申请日：2014-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brian M. Erwin ,  Eric D. Perfecto ,  Nicholas A. Polomoff ,  Jae-Woong Nah

IPC: H01L23/16 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L24/05 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/04026 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13147 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27515 ,  H01L2224/27632 ,  H01L2224/2784 ,  H01L2224/29023 ,  H01L2224/29028 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/32147 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83885 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/0665 ,  H01L2224/81805 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/27

Abstract: Electronic devices including solder bumps embedded in a pre-applied coating of underfill material and/or solder resist are fabricated, thereby improving chip-package interaction reliability. Underfill can be directly applied to a wafer, enabling increased filler loadings. Passages formed in the underfill and/or solder resist coating expose electrically conductive pads or metal pillars. Such passages can be filled with molten solder to form the solder bumps.

Abstract translation: 制造包括嵌入在预填充材料和/或阻焊剂的预涂层中的焊料凸块的电子器件，从而提高芯片封装相互作用的可靠性。 底部填充物可以直接施加到晶片上，从而增加填料的填充量。 在底部填充和/或阻焊涂层中形成的通道暴露导电垫或金属柱。 可以用熔融焊料填充这样的通道以形成焊料凸块。

公开(公告)号：US20160035641A1

公开(公告)日：2016-02-04

申请号：US14875917

申请日：2015-10-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Brian M. Erwin ,  Karen P. McLaughlin ,  Ekta Misra

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L23/3171 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76816 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/1031 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

Abstract translation: 制造半导体器件的方法包括在半导体器件的至少一个覆盖层上形成钝化层，并在钝化层上形成密封剂层。 该方法还包括图案化封装层以暴露钝化层的一部分并在钝化层中形成最终的通孔。 导电材料沉积在最终通孔中。 该方法还包括平坦化导电材料，直到到达封装层的剩余部分，使得导电材料与密封剂层齐平并且保护钝化层。