公开(公告)号：US10797049B2

公开(公告)日：2020-10-06

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

公开(公告)号：US20200027979A1

公开(公告)日：2020-01-23

申请号：US16038384

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08

Abstract: One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.

公开(公告)号：US20170330970A1

公开(公告)日：2017-11-16

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US09812573B1

公开(公告)日：2017-11-07

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US20200135723A1

公开(公告)日：2020-04-30

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.