公开(公告)号：US09484301B2

公开(公告)日：2016-11-01

申请号：US14718466

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Max G. Levy ,  Gary L. Milo ,  Matthew D. Moon ,  Anthony C. Speranza ,  Timothy D. Sullivan ,  David C. Thomas ,  Steven S. Williams

IPC: H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

公开(公告)号：US09390969B2

公开(公告)日：2016-07-12

申请号：US14600273

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： David A. DeMuynck ,  Zhong-Xiang He ,  Daniel R. Miga ,  Matthew D. Moon ,  Daniel S. Vanslette ,  Eric J. White

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，更具体地，涉及高性能电感器。 IC包括设置在基板上的电介质层内的至少一个沟槽。 沟槽被保形地涂覆有衬里和种子层，并且包括内部的互连。 互连包括在互连的侧壁上的硬掩模。