公开(公告)号：US09443857B2

公开(公告)日：2016-09-13

申请号：US14561999

申请日：2014-12-05

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  John E. Barth, Jr. ,  Edward J. Nowak

IPC: H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L31/112 ,  H01L27/12 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/10885 ,  H01L27/1203

Abstract: Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.

Abstract translation: 形成半导体器件的系统和方法。 包括深沟槽的沟槽电容器形成在n +型衬底中。 深沟槽具有部分地填充有由存储电介质包围的沟槽导体的下部。 在深沟槽的上部形成多晶硅生长。 半导体器件包括单晶半导体，其具有将多晶硅生长的一部分与深沟槽的暴露边缘分开的成角度的接缝。 字线缠绕在单晶半导体上。 位线覆盖单晶半导体。

公开(公告)号：US09299769B2

公开(公告)日：2016-03-29

申请号：US14151550

申请日：2014-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/06 ,  H01L21/76254

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract translation: 公开了形成这种结构的半导体 - 氧化物结构和相关方法。 在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

公开(公告)号：US09224437B2

公开(公告)日：2015-12-29

申请号：US14068653

申请日：2013-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John E. Barth, Jr. ,  Abraham Mathews ,  Donald W. Plass ,  Kenneth J. Reyer

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/12 ,  G11C11/4094

CPC classification number: G11C7/067 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

Abstract: A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.

Abstract translation: 单端输入读出放大器使用通过器件将输入的本地位线耦合到全局位线评估节点。 读出放大器还包括一对交叉耦合的反相器，其第一反相器具有直接耦合到全局位线评估节点的输入端。 响应于控制信号，第二反相器的输出选择性地耦合到全局位线评估节点，使得当通过器件有效时，局部位线对全局位线评估节点充电或放电而不受影响 基本上通过第二反相器的输出的状态。 当控制信号处于另一状态时，交叉耦合的反相器形成锁存器。 第二反相器的内部输出控制电路根据控制信号中断由第二反相器提供的反馈。