公开(公告)号：US20180047807A1

公开(公告)日：2018-02-15

申请号：US15233229

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Herbert L. Ho ,  Byeong Y. Kim ,  Joyce C. Liu

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/285 ,  H01L27/06 ,  H01L23/535 ,  H01L21/02

CPC classification number: H01L28/60 ,  H01L21/02271 ,  H01L27/0629 ,  H01L27/10861 ,  H01L29/945

Abstract: Device structures for a deep trench capacitor and methods of fabricating device structures for a deep trench capacitor. A dielectric layer is formed on a substrate and an opening is formed that extends from a top surface of the dielectric layer through the dielectric layer. A deep trench is formed in the substrate and is aligned with the opening in the dielectric layer. A plate of a deep trench capacitor is formed that is located at least partially inside the deep trench and at least partially inside the opening in the dielectric layer. A diffusion pad is formed that arranged at the top surface of the dielectric layer relative to the opening such that the diffusion pad is coupled with the plate of the deep trench capacitor.

公开(公告)号：US09589965B1

公开(公告)日：2017-03-07

申请号：US15004216

申请日：2016-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Melissa A. Smith ,  Sunit S. Mahajan ,  Herbert L. Ho

IPC: H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/10879

Abstract: Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.

Abstract translation: 提供了形成用于eDRAM的多晶硅填充深沟槽的方法。 该方法可以包括在衬底中形成多个多晶硅填充的深沟槽。 将外延延迟掺杂剂引入到沟槽的上部。 然后在衬底上形成多个翅片，其中每个多晶硅填充的深沟槽包括在其上延伸的对应的鳍。 至少在多晶硅填充的深沟槽上外延生长硅层。 在多晶硅填充的深沟槽中的掺杂剂用于控制硅层的外延生长，减少或防止在先进技术节点处的相邻鳍片和/或深沟槽的短路。

公开(公告)号：US10083967B2

公开(公告)日：2018-09-25

申请号：US15665979

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L21/02 ,  H01L21/8242 ,  H01L29/92 ,  H01L27/108 ,  H01L49/02 ,  H01L21/764

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US09564505B2

公开(公告)日：2017-02-07

申请号：US14254939

申请日：2014-04-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Martin M. Frank ,  Herbert L. Ho ,  Mark J. Hurley ,  Rashmi Jha ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

CPC classification number: H01L29/49 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/517

Abstract: Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Abstract translation: 提出了离子注入来改变双功能金属栅极整合的有效功函数。 一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

公开(公告)号：US09299769B2

公开(公告)日：2016-03-29

申请号：US14151550

申请日：2014-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/06 ,  H01L21/76254

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract translation: 公开了形成这种结构的半导体 - 氧化物结构和相关方法。 在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

公开(公告)号：US20170358581A1

公开(公告)日：2017-12-14

申请号：US15665979

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

公开(公告)号：US09793341B1

公开(公告)日：2017-10-17

申请号：US15170224

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Davood Shahrjerdi ,  Herbert L. Ho ,  Kangguo Cheng

IPC: H01L27/108 ,  H01L21/8242 ,  H01L49/02

CPC classification number: H01L28/92

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a deep trench capacitor, integrated structures and methods of manufacture. The structure includes: a conductive material formed on an underside of an insulator layer and which acts as a back plate of a deep trench capacitor; an inner conductive layer extending through the insulator layer and an overlying substrate; and a dielectric liner between the inner conductive material and the conductive material, and formed on a sidewall of an opening within the insulator layer and the overlying substrate.

公开(公告)号：US09754945B2

公开(公告)日：2017-09-05

申请号：US14452762

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eduard A. Cartier ,  Herbert L. Ho ,  Donghun Kang

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/92

CPC classification number: H01L27/1087 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10882 ,  H01L28/91

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.