公开(公告)号：US20190267052A1

公开(公告)日：2019-08-29

申请号：US15903826

申请日：2018-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoli HU ,  Wei ZHAO ,  Hao PU

IPC: G11C7/12 ,  G11C11/419

Abstract: A structure includes a write driver circuit configured to drive both a true bitline side and a complement bitline side up to a power supply and down to ground such that one of the true bitline side and the complement bitline side is driven to ground and another of the true bitline side and the complement bitline side is driven to a high level at a same time and before a precharge below a level of the power supply of the one of the true bitline side and the complement bitline side.

公开(公告)号：US20190109197A1

公开(公告)日：2019-04-11

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Wei ZHAO ,  Hui ZANG ,  Hong YU ,  Zhenyu HU ,  Scott BEASOR ,  Erik GEISS ,  Jerome CIAVATTI ,  Jae Gon LEE

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US20170352407A1

公开(公告)日：2017-12-07

申请号：US15175466

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI ,  Qing LI ,  Wei ZHAO ,  Xiaoli HU

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/067

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.

公开(公告)号：US20190066786A1

公开(公告)日：2019-02-28

申请号：US15684492

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI ,  Qing LI ,  Xiaoli HU ,  Wei ZHAO ,  Jieyao LIU

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C7/065 ,  G11C7/12 ,  G11C11/419 ,  G11C2207/002

Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

公开(公告)号：US20190013245A1

公开(公告)日：2019-01-10

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Wei HONG ,  Wei ZHAO ,  Tae Jeong LEE ,  Zhenyu HU

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/7855 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/475 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/435 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2027/11805 ,  H01L2027/11831 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.