公开(公告)号：US20180330995A1

公开(公告)日：2018-11-15

申请号：US16026840

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan DOU ,  Hong YU ,  Zhenyu HU ,  Xing ZHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823456 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/42376

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US20150087134A1

公开(公告)日：2015-03-26

申请号：US14032978

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hsin-Neng TAI ,  Puneet KHANNA ,  Zhenyu HU ,  Huey-Ming WANG

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate isolation region uniformity.

Abstract translation: 促进隔离区域均匀性的方法包括：图案化半导体衬底以在半导体衬底内形成至少一个隔离开口，该图案化包括至少部分地保留在半导体衬底的一部分上方的保护性硬掩模; 在所述至少一个隔离开口内和之上提供绝缘材料，以及对所述绝缘材料进行平坦化以便于制造所述半导体衬底内的隔离区域; 停止在保护性硬掩模上的平坦化，并将至少一部分保护性硬掩模暴露在半导体衬底的部分之上; 并且在所述至少一个隔离开口和所述暴露的所述半导体衬底的所述部分之上的所述暴露的保护性硬掩模之外，在所述至少一个隔离开口内留下所述绝缘材料的同时，将所述绝缘材料的剩余部分非选择性地去除， 半导体衬底，方便隔离区均匀。

公开(公告)号：US20190109197A1

公开(公告)日：2019-04-11

申请号：US15728070

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Wei ZHAO ,  Hui ZANG ,  Hong YU ,  Zhenyu HU ,  Scott BEASOR ,  Erik GEISS ,  Jerome CIAVATTI ,  Jae Gon LEE

IPC: H01L29/417 ,  H01L27/11 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.

公开(公告)号：US20160111320A1

公开(公告)日：2016-04-21

申请号：US14515628

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang SHEN ,  Zhenyu HU ,  Jin Ping LIU

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/76232 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6681

Abstract: Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

Abstract translation: 提供半导体器件和制造方法，其具有翅片结构内的隔离特征，其例如有助于隔离由鳍结构支撑的电路元件。 制造方法包括例如提供部分地设置在鳍结构内的隔离材料，隔离材料被形成为包括T形隔离区域和延伸到翅片结构中的第一部分，并且第二部分设置在 在第一部分之上并且延伸到翅片结构之上。

公开(公告)号：US20150380316A1

公开(公告)日：2015-12-31

申请号：US14319640

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  HongLiang SHEN ,  Zhao LUN ,  Zhenyu HU ,  Richard J. Carter

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

公开(公告)号：US20190013245A1

公开(公告)日：2019-01-10

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Wei HONG ,  Wei ZHAO ,  Tae Jeong LEE ,  Zhenyu HU

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/7855 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/475 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/435 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2027/11805 ,  H01L2027/11831 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.

公开(公告)号：US20180277440A1

公开(公告)日：2018-09-27

申请号：US15467536

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Zhenyu HU ,  Haiting WANG

IPC: H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.

公开(公告)号：US20170278965A1

公开(公告)日：2017-09-28

申请号：US15079142

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani PANDEY ,  Pei ZHAO ,  Zhenyu HU

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.

公开(公告)号：US20170033224A1

公开(公告)日：2017-02-02

申请号：US14812653

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Zhenyu HU ,  Hong YU ,  Jinping LIU

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/7853 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66795

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract translation: 一种方法可以包括执行蚀刻工艺以限定具有第一深度的翅片沟槽，第一深度小于翅片的目标高度。 方法还可以包括形成层以保护限定翅片沟槽的侧壁。 方法还可以包括执行第二蚀刻工艺以增加散热片沟槽的深度。

公开(公告)号：US20160315084A1

公开(公告)日：2016-10-27

申请号：US14691960

申请日：2015-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng WU ,  HongLiang SHEN ,  Changyong XIAO ,  Jianhua YIN ,  Jie CHEN ,  Jin Ping LIU ,  Hong YU ,  Zhenyu HU ,  Lan YANG ,  Wanxun HE

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L29/1033

Abstract: There is set forth herein in one embodiment a semiconductor structure having a first region and a second region. The first region can include fins of a first fin height and the second region can include fins of a second fin height.

Abstract translation: 这里在一个实施例中阐述了具有第一区域和第二区域的半导体结构。 第一区域可以包括第一翅片高度的翅片，并且第二区域可以包括具有第二翅片高度的翅片。