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    RECHARGEABLE WAFER CARRIER SYSTEMS
    1.
    发明申请
    RECHARGEABLE WAFER CARRIER SYSTEMS 审中-公开

    公开(公告)号：US20180048169A1

    公开(公告)日：2018-02-15

    申请号：US15233454

    申请日：2016-08-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Abner BELLO ,  Stephanie WAITE ,  William J. FOSNIGHT

    IPC: H02J7/00 ,  H02J50/10 ,  H01L21/677 ,  H02J7/02 ,  H01L21/67

    CPC classification number: H02J50/10 ,  H01L21/67379 ,  H01L21/67386 ,  H01L21/67396 ,  H01L21/6773 ,  H01L21/67736 ,  H01L21/67775 ,  H02J7/0044 ,  H02J7/025

    Abstract: Rechargeable wafer carrier systems and methods are provided. A rechargeable wafer carrier system includes, for instance, a housing for holding at least one wafer and at least one electronics system therein, a rechargeable power source operably connected to the housing for powering the at least one electronics system, and a charging interface for receiving a supply of power for charging the rechargeable power source. The housing may be configured for transport within an automated material handling system. Also provided are methods of charging a rechargeable wafer carrier system, which includes, for instance, providing a rechargeable wafer carrier system having at least one electronics system and a rechargeable power source, operably connecting the rechargeable wafer carrier system to a charging base, and supplying power from the charging base to the rechargeable power source.

    DECOUPLING MEASUREMENT OF LAYER THICKNESSES OF A PLURALITY OF LAYERS OF A CIRCUIT STRUCTURE
    4.
    发明申请
    DECOUPLING MEASUREMENT OF LAYER THICKNESSES OF A PLURALITY OF LAYERS OF A CIRCUIT STRUCTURE 有权
    解决电路结构层数多层厚度的测量

    公开(公告)号：US20150198435A1

    公开(公告)日：2015-07-16

    申请号：US14155504

    申请日：2014-01-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Alok VAID ,  Abner BELLO ,  Sipeng GU ,  Lokesh SUBRAMANY ,  Xiang HU ,  Akshey SEHGAL

    IPC: G01B11/06 ,  H01L21/66

    CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

    Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。

    FINFET CHANNEL STRESS USING TUNGSTEN CONTACTS IN RAISED EPITAXIAL SOURCE AND DRAIN
    5.
    发明申请
    FINFET CHANNEL STRESS USING TUNGSTEN CONTACTS IN RAISED EPITAXIAL SOURCE AND DRAIN 有权
    FINANCE通道应力使用连接的外部源和漏极中的触点

    公开(公告)号：US20140319614A1

    公开(公告)日：2014-10-30

    申请号：US13870854

    申请日：2013-04-25

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Abhijeet PAUL ,  Abner BELLO ,  Vimal K. KAMINENI ,  Derya DENIZ

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

    Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

    Abstract translation: 通过在通道上施加物理应力的结构来增强FinFET的性能。 应力通过用于源极和漏极的钨触点，外延生长的升高源和升高的漏极的组合以及钨接触沉积的方面的操作来实现，从而导致钨的固有应力的增强。 通过外延重新生长升高的源极和漏极的部分，通过蚀刻用于触点的沟槽和/或蚀刻在鳍的表面下方的较深的沟槽（和相应的更长的触点）来进一步增强应力。

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