公开(公告)号：US20200135545A1

公开(公告)日：2020-04-30

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. SRIVASTAVA ,  Sipeng GU ,  Sunil K. SINGH ,  Xinyuan DOU ,  Akshey SEHGAL ,  Zhiguo SUN

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US20190081155A1

公开(公告)日：2019-03-14

申请号：US15703221

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Kangguo CHENG ,  Nicolas LOUBET ,  Xin MIAO ,  Pietro MONTANINI ,  John ZHANG ,  Haigou HUANG ,  Jianwei PENG ,  Sipeng GU ,  Hui ZANG ,  Yi QI ,  Xusheng WU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.

公开(公告)号：US20150263169A1

公开(公告)日：2015-09-17

申请号：US14207822

申请日：2014-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng GU ,  Zhiguo SUN ,  Sandeep GAAN ,  Danni CHEN ,  Wen-Pin PENG ,  Huang LIU

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76801 ,  H01L21/76829 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Abstract translation: 提供半导体结构和制造方法，其具有桥接膜，其有助于介电材料的下层和上覆的应力诱导层的粘附。 该方法包括例如在半导体衬底上提供其中设置有至少一个栅极结构的电介质材料层; 在所述介​​电材料层上提供具有所述至少一个栅极结构的桥接膜; 并在桥接膜上提供应力诱导层。 选择桥接膜以便于通过部分地与电介质材料层形成化学键而使介电材料的下层和上覆的应力诱导层两者粘附，而不与应力诱导层形成化学键 。

公开(公告)号：US20160005598A1

公开(公告)日：2016-01-07

申请号：US14321866

申请日：2014-07-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng GU ,  Sandeep GAAN ,  Zhiguo SUN ,  Huang LIU ,  Adam SELSLEY

IPC: H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/321

Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Abstract translation: 提供了一种用于制造分层电路结构的方法，其包括例如：在衬底上沉积第一材料层，第一材料层具有氧化的上表面; 在所述第一材料层的氧化的上表面上提供第二材料层; 并且在第二材料层在第一材料层的氧化的上表面上提供第二材料层期间，抑制一个或多个元件从第一材料层的氧化的上表面扩散到第一材料层或第二材料层中。 抑制可以包括一个或多个修饰第一材料层的特征，在第一材料层的氧化的上表面上形成保护层，或改变在提供第二材料层中使用的至少一个工艺参数。

公开(公告)号：US20150380246A1

公开(公告)日：2015-12-31

申请号：US14315659

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang HU ,  Yuping REN ,  Duohui BEI ,  Sipeng GU ,  Huang LIU

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/538

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract translation: 提供了用于在电路结构上的尺寸控制的通孔形成的方法，包括在多个相邻的导电结构上。 所述方法包括例如在电路结构之上提供图案化的多层堆叠结构，所述堆叠结构包括至少一层，以及在所述至少一层上方的图案转移层，所述图案转移层被图案化 至少有一个通孔; 在所述至少一个通孔开口内提供侧壁间隔层，以形成至少一个尺寸控制的通孔开口; 以及使用所述至少一个尺寸控制的通孔开口蚀刻穿过所述堆叠结构的所述至少一个层，以便于在所述电路结构上提供通孔。 在一个实施方案中，堆叠结构包括设置在电介质层和平坦化层之间的图案化硬掩模层内的沟槽开口，并且通孔部分地自对准沟槽。

公开(公告)号：US20160099171A1

公开(公告)日：2016-04-07

申请号：US14969154

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Yuping REN ,  Duohui BEI ,  Sipeng GU ,  Huang LIU

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

公开(公告)号：US20150198435A1

公开(公告)日：2015-07-16

申请号：US14155504

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alok VAID ,  Abner BELLO ,  Sipeng GU ,  Lokesh SUBRAMANY ,  Xiang HU ,  Akshey SEHGAL

IPC: G01B11/06 ,  H01L21/66

CPC classification number: H01L22/12 ,  G01B11/02 ,  G01B11/0633 ,  G01B11/065 ,  G01B2210/56 ,  G01N21/211 ,  G03F7/70616 ,  G03F7/70625

Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.

Abstract translation: 获得电路结构层的厚度的测量，其中使用光学临界尺寸（OCD）测量技术测量层的厚度，并且层包括高k层和界面层。 分别获得高k层的厚度的测量，其中使用来自OCD测量技术的单独的测量技术来测量高k层的厚度。 与OCD测量技术相比，单独的测量技术提供了来自层的界面层厚度的信号的高k层厚度的信号的更大的去耦。 电路结构的特性，如界面层的厚度，部分使用单独获得的高k层的厚度测量来确定。