公开(公告)号：US20160190304A1

公开(公告)日：2016-06-30

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre MORIN ,  Kangguo CHENG ,  Jody FRONHEISER ,  Xiuyu CAI ,  Juntao LI ,  Shogo MOCHIZUKI ,  Ruilong XIE ,  Hong HE ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7849

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract translation: 具有基本上无缺陷的SiGe应变松弛缓冲层的改性硅衬底适用于构建高性能CMOS FinFET器件的基础。 可以通过切割或分割应变的外延膜来形成基本上无缺陷的SiGe应变松弛缓冲层，使得薄膜段的边缘经历弹性应变弛豫。 当片段足够小时，整个膜被松弛，使得膜基本上没有位错缺陷。 一旦形成了基本上无缺陷的应变松弛缓冲层，则可以从松弛的SRB层外延生长应变通道层。 然后将应变通道层图案化以产生用于FinFET器件的鳍片。 在一个实施例中，形成双应变通道层 - 用于NFET器件的拉伸应变层，以及用于PFET器件的压缩应变层。

公开(公告)号：US20180006155A1

公开(公告)日：2018-01-04

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson HOLT ,  Jinping LIU ,  Jody FRONHEISER ,  Bharat KRISHNAN ,  Churamani GAIRE ,  Timothy James MCARDLE ,  Murat Kerem AKARVARDAR

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US20180005826A1

公开(公告)日：2018-01-04

申请号：US15198570

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey P. JACOB ,  Jody FRONHEISER ,  Bruce DORIS ,  Huiming BU

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0638 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/66795

Abstract: A method of preventing corner rounding for an alternate channel FINFET formed in trenches and the resulting devices are provided. Embodiments include providing a Si substrate; forming a trench in the Si substrate; forming a Si based layer with a flat upper surface in the trench; and forming a SiGe layer over the Si based layer.

公开(公告)号：US20150340471A1

公开(公告)日：2015-11-26

申请号：US14286400

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong LIM ,  Jody FRONHEISER ,  Christopher PRINDLE

IPC: H01L29/66 ,  H01L29/08

CPC classification number: H01L29/0847 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.

Abstract translation: 提供通过部分EPI生长形成凸起S / D区域的方法，其中部分EPI衬垫在其间，并且提供所得到的装置。 实施例包括形成在STI层上延伸的翅片组; 在翅片组上形成一个门; 在栅极的每一侧上形成栅极间隔物; 在所述翅片组的每个翅片上形成靠近每个间隔件的凸起S / D区域，每个凸起的S / D区域具有顶表面，垂直侧壁和下表面; 在每个凸起的S / D区域之间和之间形成衬垫; 从每个凸起的S / D区域的顶表面和一组翅片之间移除衬垫; 在每个凸起的S / D区域的上表面上形成过度生长区域; 在升高的S / D区域之间形成ILD; 并通过ILD形成接触，直到升高的S / D区域。

公开(公告)号：US20170047425A1

公开(公告)日：2017-02-16

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven BENTLEY ,  Jody FRONHEISER ,  Xin MIAO ,  Joseph WASHINGTON ,  Pierre MORIN

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

Abstract translation: 提供了一种执行早期PTS植入和在体或鳍通道下形成缓冲层以控制沟道中的掺杂并且产生的体或鳍器件的方法。 实施例包括在基板中形成凹部; 在所述凹部的底表面下方形成PTS层; 在所述凹部的底表面和侧表面上形成缓冲层; 在缓冲层上和邻近缓冲层上形成沟道层; 并对通道，缓冲器和PTS层进行退火。

公开(公告)号：US20160056238A1

公开(公告)日：2016-02-25

申请号：US14933501

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong LIM ,  Jody FRONHEISER ,  Christopher PRINDLE

IPC: H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming raised S/D regions by partial EPI growth with a partial EPI liner therebetween and the resulting device are provided. Embodiments include forming groups of fins extending above a STI layer; forming a gate over the groups of fins; forming a gate spacer on each side of the gate; forming a raised S/D region proximate to each spacer on each fin of the groups of fins, each raised S/D region having a top surface, vertical sidewalls, and an undersurface; forming a liner over and between each raised S/D region; removing the liner from the top surface of each raised S/D region and from in between a group of fins; forming an overgrowth region on the top surface of each raised S/D region; forming an ILD over and between the raised S/D regions; and forming a contact through the ILD, down to the raised S/D regions.