公开(公告)号：US09812324B1

公开(公告)日：2017-11-07

申请号：US15405789

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Zhuang ,  Lars Liebmann ,  Stuart A. Sieg ,  Fee Li Lie ,  Mahender Kumar ,  Shreesh Narasimha ,  Ahmed Hassan ,  Guillaume Bouche ,  Xintuo Dai

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/30 ,  H01L21/027 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.

公开(公告)号：US10768521B2

公开(公告)日：2020-09-08

申请号：US15876540

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amr Y. Abdo ,  Lei Zhuang ,  Jed H. Rankin

IPC: G03F1/24 ,  G03F1/58 ,  G03F1/38

Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

公开(公告)号：US09799660B1

公开(公告)日：2017-10-24

申请号：US15151622

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert C. Wong ,  Lei Zhuang ,  Ananthan Raghunathan

IPC: H01L27/11 ,  H01L21/56 ,  H01L21/308 ,  H01L21/3065 ,  H01L23/31

CPC classification number: H01L27/1104 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/56 ,  H01L23/3171 ,  H01L27/0207

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

公开(公告)号：US09899183B1

公开(公告)日：2018-02-20

申请号：US15222096

申请日：2016-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Zhuang ,  Timothy A. Brunner

IPC: G03F9/00 ,  G03B27/62 ,  G03B27/42 ,  H01J37/26

CPC classification number: H01J37/26

Abstract: Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.

公开(公告)号：US10366996B2

公开(公告)日：2019-07-30

申请号：US15704598

申请日：2017-09-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert C. Wong ,  Lei Zhuang ,  Ananthan Raghunathan

IPC: H01L27/11 ,  H01L23/31 ,  H01L21/56 ,  H01L21/308 ,  H01L21/3065 ,  H01L27/02

Abstract: Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.

公开(公告)号：US20190227427A1

公开(公告)日：2019-07-25

申请号：US15876540

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amr Y. Abdo ,  Lei Zhuang ,  Jed H. Rankin

IPC: G03F1/24 ,  G03F1/38 ,  G03F1/58

Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

公开(公告)号：US20180033590A1

公开(公告)日：2018-02-01

申请号：US15222096

申请日：2016-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Zhuang ,  Timothy A. Brunner

IPC: H01J37/26

CPC classification number: H01J37/26

Abstract: Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.