公开(公告)号：US10263099B2

公开(公告)日：2019-04-16

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/51

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US10170591B2

公开(公告)日：2019-01-01

申请号：US15178871

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20180174855A1

公开(公告)日：2018-06-21

申请号：US15890859

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US20170358662A1

公开(公告)日：2017-12-14

申请号：US15178871

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US09653571B2

公开(公告)日：2017-05-16

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

公开(公告)号：US20170092721A1

公开(公告)日：2017-03-30

申请号：US15363607

申请日：2016-11-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/06 ,  H01L27/088

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US10475660B2

公开(公告)日：2019-11-12

申请号：US15363607

申请日：2016-11-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/30 ,  H01L21/31 ,  H01L21/82 ,  H01L21/762 ,  H01L29/06 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/027 ,  H01L21/033

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US10297510B1

公开(公告)日：2019-05-21

申请号：US15962536

申请日：2018-04-25

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Soon-Cheon Seo ,  Fee Li Lie ,  Linus Jang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A method for fabricating a multiple gate width structure for an integrated circuit is described. A fin on a semiconductor substrate with a first hard mask layer is covered by a first and second sacrificial gate each of which includes a second hard mask layer. Spacer layers and a dielectric layer are formed over the first and second sacrificial gate structures. The resulting structure is planarized so that the first and second sacrificial gate structures and the dielectric layer have coplanar top surfaces. The first and second sacrificial gate structures are removed to respectively form first and second trench recesses in the dielectric layer. The trench recesses are filled with a conductor to form permanent gate structures. A first permanent gate structure is formed in the first trench recess has a first length and a second permanent gate structure is formed in the second trench recess has a second length greater than the first length.

公开(公告)号：US20160365425A1

公开(公告)日：2016-12-15

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  Globalfoundries Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract translation: 本发明的一个方面包括具有用于侧壁图像转印过程的亚光刻尺寸的独立间隔物。 独立间隔件包括：第一间隔层，其具有设置在半导体层上的第一部分; 以及第二间隔层，其具有设置在第一间隔层的第一部分上的第一表面，其中第一间隔层具有第一介电常数，第二间隔层具有第二介电常数，第一介电常数大于第二间隔层 介电常数，并且其中第一和第二间隔层中的每一个的尺寸共同确定独立间隔物的亚光刻横向尺寸。

公开(公告)号：US10593782B2

公开(公告)日：2020-03-17

申请号：US16056934

申请日：2018-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/51

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.