公开(公告)号：US10566328B2

公开(公告)日：2020-02-18

申请号：US15904555

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bala Haran ,  Christopher Sheraw ,  Mahender Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/311

Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.

公开(公告)号：US10461186B1

公开(公告)日：2019-10-29

申请号：US15994392

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Ruilong Xie ,  Mahender Kumar

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

Abstract: Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.

公开(公告)号：US09812324B1

公开(公告)日：2017-11-07

申请号：US15405789

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Zhuang ,  Lars Liebmann ,  Stuart A. Sieg ,  Fee Li Lie ,  Mahender Kumar ,  Shreesh Narasimha ,  Ahmed Hassan ,  Guillaume Bouche ,  Xintuo Dai

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/30 ,  H01L21/027 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.

公开(公告)号：US09780002B1

公开(公告)日：2017-10-03

申请号：US15173766

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Brian Greene ,  Mahender Kumar ,  Daniel J. Dechene ,  Daniel Jaeger

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L21/26506 ,  H01L21/02118 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.

公开(公告)号：US20190267371A1

公开(公告)日：2019-08-29

申请号：US15904555

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bala Haran ,  Christopher Sheraw ,  Mahender Kumar

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/02

Abstract: One illustrative integrated circuit product disclosed herein includes a plurality of FinFET transistor devices, a plurality of fins, each of the fins having an upper surface, and an elevated isolation structure having an upper surface that is positioned at a level that is above a level of the upper surface of the fins. In this example, the product also includes a first gate structure having an axial length in a direction corresponding to the gate width direction of the transistor devices, wherein at least a portion of the axial length of the first gate structure is positioned above the upper surface of the elevated isolation structure.