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    Integrated magnetic random access memory with logic device
    1.
    发明授权
    Integrated magnetic random access memory with logic device 有权

    公开(公告)号：US10199572B2

    公开(公告)日：2019-02-05

    申请号：US15164914

    申请日：2016-05-26

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Wanbing Yi ,  Yi Jiang ,  Daxiang Wang ,  Wei Shao ,  Juan Boon Tan

    IPC分类号： H01L43/12 ,  H01L27/22

    摘要： Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

    Device without zero mark layer
    2.
    发明授权
    Device without zero mark layer 有权

    公开(公告)号：US09773702B2

    公开(公告)日：2017-09-26

    申请号：US14981873

    申请日：2015-12-28

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Shunqiang Gong ,  Juan Boon Tan ,  Shijie Wang ,  Mahesh Bhatkar ,  Daxiang Wang

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/544 ,  H01L23/525

    CPC分类号： H01L21/76898 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

    Device without zero mark layer
    3.
    发明授权
    Device without zero mark layer 有权

    公开(公告)号：US10553488B2

    公开(公告)日：2020-02-04

    申请号：US15710854

    申请日：2017-09-21

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Shunqiang Gong ,  Juan Boon Tan ,  Shijie Wang ,  Mahesh Bhatkar ,  Daxiang Wang

    IPC分类号： H01L23/544 ,  H01L23/525 ,  H01L21/768

    摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

    DEVICE WITHOUT ZERO MARK LAYER
    6.
    发明申请
    DEVICE WITHOUT ZERO MARK LAYER 有权
    没有零标记层的设备

    公开(公告)号：US20160190041A1

    公开(公告)日：2016-06-30

    申请号：US14981873

    申请日：2015-12-28

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Shunqiang Gong ,  Juan Boon Tan ,  Shijie Wang ,  Mahesh Bhatkar ,  Daxiang Wang

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/544 ,  H01L23/528

    CPC分类号： H01L21/76898 ,  H01L23/525 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

    摘要翻译： 公开了用于形成装置的装置和方法。 该方法包括提供具有第一表面和第二表面的基底。 在衬底中形成至少一个通硅通孔（TSV）开口。 TSV开口延伸穿过衬底的第一和第二表面。 在基板上形成与对准标记对应的对准沟槽。 对准沟槽从衬底的第一表面延伸到比TSV开口的深度浅的深度。 介电衬里层设置在衬底上。 电介质衬垫层至少对TSV开口的侧壁进行排列。 导电层设置在衬底上。 导电层填充至少TSV开口以形成TSV接触。 在衬底上形成再分布层（RDL）。 使用掩模版图案化RDL层以形成对应于TSV接触焊盘的至少一个开口。 使用衬底中的对准标记对准标线。