公开(公告)号：US10121964B2

公开(公告)日：2018-11-06

申请号：US14862180

申请日：2015-09-23

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Juan Boon Tan ,  Yi Jiang ,  Daxiang Wang ,  Fan Zhang ,  Francis Poh ,  Danny Pak-Chum Shum

IPC分类号： H01L43/12 ,  H01L27/22 ,  H01L43/08

摘要： Integrating magnetic random access memory with logic is disclosed. The magnetic tunnel junction stack of a magnetic memory cell is disposed within a dielectric layer which serves as a via level of an interlevel dielectric layer with a metal level above the via level. An integration scheme for forming dual damascene structures for interconnects can be formed to logic and memory cells easily.

公开(公告)号：US20150311251A1

公开(公告)日：2015-10-29

申请号：US14261543

申请日：2014-04-25

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： WANBING YI ,  YANG HONG ,  YI JIANG ,  Francis Poh ,  Tze Ho Simon Chan ,  Juan Boon Tan

IPC分类号： H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L27/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

摘要翻译： 一种制造集成电路的方法包括在钝化层上方和钝化层的沟槽内沉积底部电极层，MTJ层和顶部电极层，并且去除MTJ层和顶部电极层的部分以形成 MTJ /顶部电极堆叠在底部电极层上方，并且至少部分地在沟槽的部分内被所述去除重新打开。 该方法还包括在MTJ /顶部电极堆叠上形成另外的钝化层，形成另外的钝化层的另外的ILD层，以及在ILD层上和MTJ /顶部电极堆叠上重整顶部电极层。 此外，该方法包括去除底部电极层，另外的钝化层，另外的ILD层和重新形成的顶部电极层的部分，以形成底部电极/ MTJ /顶部电极堆叠。

公开(公告)号：US09349772B2

公开(公告)日：2016-05-24

申请号：US14261543

申请日：2014-04-25

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Wanbing Yi ,  Yang Hong ,  Yi Jiang ,  Francis Poh ,  Tze Ho Simon Chan ,  Juan Boon Tan

IPC分类号： H01L27/10 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

CPC分类号： H01L27/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

摘要翻译： 一种制造集成电路的方法包括在钝化层上方和钝化层的沟槽内沉积底部电极层，MTJ层和顶部电极层，并且去除MTJ层和顶部电极层的部分以形成 MTJ /顶部电极堆叠在底部电极层上方，并且至少部分地在沟槽的部分内被所述去除重新打开。 该方法还包括在MTJ /顶部电极堆叠上形成另外的钝化层，形成另外的钝化层的另外的ILD层，以及在ILD层上和MTJ /顶部电极堆叠上重整顶部电极层。 此外，该方法包括去除底部电极层，另外的钝化层，另外的ILD层和重新形成的顶部电极层的部分，以形成底部电极/ MTJ /顶部电极堆叠。

公开(公告)号：US09515152B2

公开(公告)日：2016-12-06

申请号：US14684311

申请日：2015-04-10

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Pengfei Guo ,  Shyue Seng Tan ,  Guowei Zhang ,  Francis Poh ,  Danny Pak-Chum Shum

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04

CPC分类号： H01L29/42328 ,  G11C16/0433 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66575 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

摘要： Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate. A floating gate is disposed over a transistor well. A control gate disposed over a control well is coupled to the floating gate. The control gate includes a control capacitor. A non-self-aligned source/drain (S/D) region is disposed within the transistor well and serves as an erase terminal.

摘要翻译： 提出了一种用于非易失性存储单元的简单且无成本的多时间可编程（MTP）结构的实施例。 存储单元包括基板。 浮置栅极位于晶体管的上方。 设置在控制井上的控制栅极耦合到浮动栅极。 控制栅极包括一个控制电容器。 非自对准源极/漏极（S / D）区域设置在晶体管阱内并用作擦除端子。

公开(公告)号：US09165610B1

公开(公告)日：2015-10-20

申请号：US14318766

申请日：2014-06-30

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Francis Poh ,  Shifeng Zhao ,  Yang Hong ,  Tze Ho Simon Chan

IPC分类号： G11C11/02 ,  G11C13/00 ,  G11C5/06 ,  G11C11/40 ,  G11C8/00 ,  G11C5/02 ,  G11C8/14 ,  H01L27/24 ,  G11C7/18

CPC分类号： G11C13/003 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  G11C8/14 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0028 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436

摘要： Disclosed herein are memory cell arrays, semiconductor devices, and methods for fabricating semiconductor devices. In one embodiment, a memory cell array includes first, second, third, and fourth memory cells each having a first transistor and a second transistor. First and second word-lines are coupled with the gates of the first transistors of the first and second memory cells. The second and a third word-line are coupled with the gates of the second transistors of the third and fourth memory cells.

摘要翻译： 这里公开的是存储单元阵列，半导体器件和用于制造半导体器件的方法。 在一个实施例中，存储单元阵列包括每个具有第一晶体管和第二晶体管的第一，第二，第三和第四存储单元。 第一和第二字线与第一和第二存储器单元的第一晶体管的栅极耦合。 第二和第三字线与第三和第四存储器单元的第二晶体管的栅极耦合。