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公开(公告)号：US10199342B2
公开(公告)日：2019-02-05
申请号：US15412067
申请日：2017-01-23
发明人： Xiaohua Zhan , Xinfu Liu , Yoke Leng Lim , Siow Lee Chwa
IPC分类号： H01L23/00 , H01L21/768 , H01L21/02 , H01L23/498 , H01L23/31
摘要： A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.
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公开(公告)号：US09349654B2
公开(公告)日：2016-05-24
申请号：US14228258
申请日：2014-03-28
发明人： Liang Li , Xuesong Rao , Martina Damayanti , Wei Lu , Alex See , Yoke Leng Lim
IPC分类号： H01L21/8234 , H01L21/311 , H01L21/28 , H01L29/06 , H01L21/762 , H01L27/115
CPC分类号： H01L21/823481 , H01L21/28229 , H01L21/28273 , H01L21/31111 , H01L21/31144 , H01L21/762 , H01L21/76224 , H01L27/11526 , H01L27/11546 , H01L29/0649
摘要： Device and a method of forming a device are presented. The method includes providing a substrate prepared with isolation regions. The substrate includes first, second and third regions. The first region includes a memory region, the second region includes a high voltage (HV) region and the third region includes a logic region. An additional dielectric layer covering the substrate and the isolation regions is formed. A first select region is selectively processed while protecting first non-select regions. The first select region is one of the first, second and third device regions. A first gate dielectric is formed on the select region. Top substrate active area and isolation regions of the first non-select regions are not exposed during processing of the first select region and forming the first gate dielectric.
摘要翻译： 介绍了器件和形成器件的方法。 该方法包括提供用隔离区制备的底物。 衬底包括第一，第二和第三区域。 第一区域包括存储区域，第二区域包括高电压（HV）区域，第三区域包括逻辑区域。 形成覆盖基板和隔离区域的附加电介质层。 选择性地处理第一选择区域，同时保护第一非选择区域。 第一选择区域是第一，第二和第三设备区域之一。 在选择区域上形成第一栅极电介质。 第一非选择区域的顶部衬底有源面积和隔离区域在第一选择区域的处理期间不暴露并形成第一栅极电介质。
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公开(公告)号：US20140252445A1
公开(公告)日：2014-09-11
申请号：US13788174
申请日：2013-03-07
发明人： Yu Chen , Huajun Liu , Siow Lee Chwa , Soh Yun Siah , Yanxia Shao , Yoke Leng Lim
IPC分类号： H01L21/283 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/0332 , H01L21/28273 , H01L21/3213 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66825
摘要： Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.
摘要翻译： 公开了一种细长分裂栅极电池的制造和所得到的器件。 实施例包括在基板上形成第一栅极，第一栅极具有上表面和覆盖上表面的硬掩模，在第一栅极和硬掩模的侧表面上形成间隔隔离层，形成第二栅极 第一栅极的一侧，第二栅极的最上部点在第一栅极的上表面下方，去除硬掩模，在暴露的垂直表面上形成间隔物，并在第一和第二栅极的暴露表面上形成硅化物 。
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4.发明公开公开(公告)号：US20240297238A1
公开(公告)日：2024-09-05
申请号：US18177251
申请日：2023-03-02
IPC分类号： H01L29/66 , H01L21/8234 , H01L23/528
CPC分类号： H01L29/6656 , H01L21/823468 , H01L23/5283
摘要： A structure includes a first metal structure including a first upper metal feature having a first sidewall spacer thereabout, and a first lower metal feature under the first upper metal feature. The first lower metal feature includes a sidewall devoid of the first sidewall spacer. The structure also includes a second metal structure spaced from the first metal structure. The second metal structure includes a second upper metal feature having a second sidewall spacer thereabout, and a second lower metal feature under the first upper metal feature. The second lower metal feature includes a sidewall devoid of the second sidewall spacer. A dielectric is between the first metal structure and the second metal structure. The dielectric is devoid of any voids therein, and the opening it fills has a high aspect ratio. A related method is also provided.
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公开(公告)号：US09111866B2
公开(公告)日：2015-08-18
申请号：US13788174
申请日：2013-03-07
发明人： Yu Chen , Huajun Liu , Siow Lee Chwa , Soh Yun Siah , Yanxia Shao , Yoke Leng Lim
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/0332 , H01L21/28273 , H01L21/3213 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66825
摘要： Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.
摘要翻译： 公开了一种细长分裂栅极电池的制造和所得到的器件。 实施例包括在基板上形成第一栅极，第一栅极具有上表面和覆盖上表面的硬掩模，在第一栅极和硬掩模的侧表面上形成间隔隔离层，形成第二栅极 第一栅极的一侧，第二栅极的最上部点在第一栅极的上表面下方，去除硬掩模，在暴露的垂直表面上形成间隔物，并在第一和第二栅极的暴露表面上形成硅化物 。
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公开(公告)号：US10475803B2
公开(公告)日：2019-11-12
申请号：US15947488
申请日：2018-04-06
发明人： Anson Heryanto , Eng Huat Toh , Yongshun Sun , Yoke Leng Lim , Siow Lee Chwa
IPC分类号： H01L21/336 , H01L27/11524 , H01L21/8239 , H01L27/11558
摘要： Method for forming a memory device are disclosed. Embodiments include forming memory cells over a substrate, each memory cell includes a control gate (CG) formed over a floating gate (FG) and a select gate (SG) formed adjacent to a first side of the CG and FG, wherein a vertical oxide layer is formed between the SG and the CG and FG, forming an implant mask layer over a portion of the SG, CG and vertical oxide of each memory cell; and implanting dopants into the substrate using the implant mask to form source drain (S/D) regions between the memory cells.
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公开(公告)号：US09876019B1
公开(公告)日：2018-01-23
申请号：US15209102
申请日：2016-07-13
发明人： Xiong Zhang , Sunny Sadana , Yudi Setiawan , Yoke Leng Lim , Siow Lee Chwa
IPC分类号： H01L21/02 , H01L27/11521 , H01L21/762 , H01L29/06 , H01L21/28 , H01L21/311 , H01L29/423 , H01L29/66 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L29/42328 , H01L29/66825
摘要： Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.
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公开(公告)号：US20180019249A1
公开(公告)日：2018-01-18
申请号：US15209102
申请日：2016-07-13
发明人： Xiong Zhang , Sunny Sadana , Yudi Setiawan , Yoke Leng Lim , Siow Lee Chwa
IPC分类号： H01L29/788 , H01L29/423 , H01L21/762 , H01L21/02 , H01L21/311 , H01L21/28 , H01L29/66 , H01L29/06
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L29/42328 , H01L29/66825
摘要： Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.
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公开(公告)号：US09236391B2
公开(公告)日：2016-01-12
申请号：US14732867
申请日：2015-06-08
发明人： Yu Chen , Huajun Liu , Siow Lee Chwa , Soh Yun Siah , Yanxia Shao , Yoke Leng Lim
IPC分类号： H01L29/00 , H01L27/115 , H01L21/28 , H01L29/423 , H01L29/66 , H01L21/033 , H01L21/3213
CPC分类号： H01L27/11521 , H01L21/0332 , H01L21/28273 , H01L21/3213 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66825
摘要： Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.
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