公开(公告)号：US20240395932A1

公开(公告)日：2024-11-28

申请号：US18322212

申请日：2023-05-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： John L. LEMON ,  Hong YU ,  Haiting WANG ,  Hui ZHAN

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wraparound gate structure and methods of manufacture. The structure includes: a channel region comprising semiconductor material; an isolation structure surrounding the channel region; a divot within the isolation structure; and a gate structure comprising gate material within the divot and surrounding the channel region.

公开(公告)号：US20210151581A1

公开(公告)日：2021-05-20

申请号：US16688267

申请日：2019-11-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting WANG ,  Hong YU ,  Zhenyu HU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/762

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US20250040167A1

公开(公告)日：2025-01-30

申请号：US18225907

申请日：2023-07-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. JAIN ,  Romain H. A. FEUILLETTE ,  David C. PRITCHARD ,  James P. MAZZA ,  Hong YU

IPC: H01L29/775 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate-all-around field effect transistors and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding the plurality of semiconductor nanosheets; a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures; an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

公开(公告)号：US20210234034A1

公开(公告)日：2021-07-29

申请号：US16751779

申请日：2020-01-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yanping SHEN ,  Haiting WANG ,  Hong YU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scheme of active and dummy fin structures and methods of manufacture. The structure includes: an active fin structure; at least one dummy fin structure running along at least one side of the active fin structure along its length; a fin cut separating the at least one dummy fin structure along its longitudinal axes; and a gate structure extending over the active fin structure and the fin cut.

公开(公告)号：US20230395715A1

公开(公告)日：2023-12-07

申请号：US17830678

申请日：2022-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting WANG ,  Hong YU ,  Zhenyu HU

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7838 ,  H01L29/0847 ,  H01L29/785 ,  H01L29/66795

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a multi-channel replacement metal gate device and methods of manufacture. The structure includes: a fully depleted semiconductor on insulator substrate; a plurality of fin structures over the fully depleted semiconductor on insulator substrate; and a metal gate structure spanning over the plurality of fin structures and the fully depleted semiconductor on insulator substrate.

公开(公告)号：US20230299181A1

公开(公告)日：2023-09-21

申请号：US18324489

申请日：2023-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting WANG ,  Hong YU ,  Zhenyu HU

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/45 ,  H01L21/285 ,  H01L29/417

CPC classification number: H01L29/6681 ,  H01L29/7851 ,  H01L29/0653 ,  H01L21/76224 ,  H01L29/45 ,  H01L21/28518 ,  H01L29/41791

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US20240429237A1

公开(公告)日：2024-12-26

申请号：US18340463

申请日：2023-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton TOKRANOV ,  Man GU ,  Eric Scott KOZARSKY ,  George MULFINGER ,  Hong YU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

公开(公告)号：US20250089317A1

公开(公告)日：2025-03-13

申请号：US18463889

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong YU ,  William J. TAYLOR, JR.

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with a bottom epitaxial semiconductor material and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets; a plurality of gate structures surrounding individual semiconductor nanosheets of the plurality of semiconductor nanosheets; a first semiconductor material of a first conductivity type at source/drain regions of the plurality of gate structures; and a second semiconductor material of a second conductivity type above the first semiconductor material, the first conductivity type being different than the second conductivity type.