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    Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
    1.
    发明授权
    Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation 有权
    使用动态部分二进制翻译实现高性能ISA虚拟化的方法和装置

    公开(公告)号：US09141361B2

    公开(公告)日：2015-09-22

    申请号：US13632089

    申请日：2012-09-30

    申请人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

    发明人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

    IPC分类号： G06F9/30 ,  G06F9/45 ,  G06F9/455 ,  G06F11/36

    CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

    摘要： Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

    摘要翻译： 公开了用于本地指令集的虚拟化的方法，装置和系统。 实施例包括执行本地指令的处理器核心和第二核心，或者替代地，只有第二处理器核心在执行排除本地指令集的部分的第二指令集时消耗较少的功率。 第二核心解码器检测第二指令集的无效操作码。 微码层拆解器确定是否应翻译操作码。 翻译运行时环境识别包含第二指令集的无效操作码，其他无效操作码和中间有效操作码的可执行区域。 分析单元在执行无效操作码之前确定初始机器状态。 生成可执行区域的部分翻译，其中包括无效操作码的翻译和机器状态的状态恢复的封装，并将其保存到翻译高速缓冲存储器。

    METHOD AND APPARATUS FOR PERFORMANCE EFFICIENT ISA VIRTUALIZATION USING DYNAMIC PARTIAL BINARY TRANSLATION
    3.
    发明申请
    METHOD AND APPARATUS FOR PERFORMANCE EFFICIENT ISA VIRTUALIZATION USING DYNAMIC PARTIAL BINARY TRANSLATION 有权
    使用动态部分二进制翻译执行有效的ISA虚拟化的方法和装置

    公开(公告)号：US20140095832A1

    公开(公告)日：2014-04-03

    申请号：US13632089

    申请日：2012-09-30

    申请人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

    发明人： Gadi Haber ,  Konstantin Kostya Levit-Gurevich ,  Esfir Natanzon ,  Boris Ginzburg ,  Aya Elhanan ,  Moshe Maury Bach ,  Igor Breger

    IPC分类号： G06F9/30 ,  G06F9/312

    CPC分类号： G06F9/30181 ,  G06F8/52 ,  G06F9/30145 ,  G06F9/45558 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/452

    摘要： Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

    摘要翻译： 公开了用于本地指令集的虚拟化的方法，装置和系统。 实施例包括执行本地指令的处理器核心和第二核心，或者替代地，只有第二处理器核心在执行排除本地指令集的部分的第二指令集时消耗较少的功率。 第二核心解码器检测第二指令集的无效操作码。 微码层拆解器确定是否应翻译操作码。 翻译运行时环境识别包含第二指令集的无效操作码，其他无效操作码和中间有效操作码的可执行区域。 分析单元在执行无效操作码之前确定初始机器状态。 生成可执行区域的部分翻译，其中包括无效操作码的翻译和机器状态的状态恢复的封装，并将其保存到翻译高速缓冲存储器。

    Aggregated page fault signaling and handline
    9.
    发明授权
    Aggregated page fault signaling and handline 有权

    公开(公告)号：US09891980B2

    公开(公告)日：2018-02-13

    申请号：US13977106

    申请日：2011-12-29

    申请人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    发明人： Boris Ginzburg ,  Ronny Ronen ,  Ilya Osadchiy

    IPC分类号： G06F11/07 ,  G06F9/30 ,  G06F12/08

    CPC分类号： G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

    摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.