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    Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers
    2.
    发明授权
    Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers 有权
    芯片封装结构及其方法，将芯片粘附到框架上并形成UBM层

    公开(公告)号：US07888783B2

    公开(公告)日：2011-02-15

    申请号：US12715778

    申请日：2010-03-02

    申请人： Geng-Shin Shen ,  Yu-Ren Chen

    发明人： Geng-Shin Shen ,  Yu-Ren Chen

    IPC分类号： H01L21/44 ,  H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L23/49541 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/03

    摘要： A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces.

    摘要翻译： 芯片封装结构包括其上具有粘合剂层的芯片放置的框架; 芯片包括在其上的活性表面上的多个焊盘，并且设置在粘合剂层上; 封装结构被覆盖在芯片放置的框架的四边周围，并且封装结构的高度大于芯片的高度; 多个图案化的金属迹线电连接到多个焊盘，另一端延伸以覆盖封装结构的表面; 图案化的保护层被覆盖在图案化的金属迹线上，并且图案化的金属迹线的另一端被暴露; 在图案化的金属迹线的延伸表面上形成多个图案化的UBM层; 并且多个导电元件形成在图案化的UBM层上并且电连接到图案化金属迹线的暴露部分的一端。

    Method for fabricating multi-chip stacked package
    8.
    发明授权
    Method for fabricating multi-chip stacked package 有权
    制造多芯片堆叠封装的方法

    公开(公告)号：US07919358B2

    公开(公告)日：2011-04-05

    申请号：US12134336

    申请日：2008-06-06

    申请人： Geng-Shin Shen ,  Yu-Ren Chen

    发明人： Geng-Shin Shen ,  Yu-Ren Chen

    IPC分类号： H01L21/00

    CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed.

    摘要翻译： 包括提供引线框架的多芯片堆叠封装方法包括由多个内引线和多个外引线形成的顶表面和反面; 将第一芯片固定在引线框架的相反表面上，并且第一芯片的有效表面包括多个靠近中心区域的第一焊盘; 形成多个第一金属线，并且所述第一焊盘通过所述第一金属线电连接到所述第一内引线和所述第二内引线; 在引线框架的散热片上形成多个金属间隔物; 固定第二芯片以电连接到第一内引线和第二内引线的顶表面; 形成多个第二金属线，并且所述第二焊盘电连接到所述第一内引线和所述第二内引线的顶表面; 并且使模制件流动以形成覆盖第一芯片的封装材料，第一金属线，第二芯片，第二金属线，第一内引线和第二内引线以及外引线露出。

    Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers
    9.
    发明授权
    Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers 有权
    芯片封装结构及其方法，将芯片粘附到框架上并形成UBM层

    公开(公告)号：US07700412B2

    公开(公告)日：2010-04-20

    申请号：US12325303

    申请日：2008-12-01

    申请人： Geng-Shin Shen ,  Yu-Ren Chen

    发明人： Geng-Shin Shen ,  Yu-Ren Chen

    IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC分类号： H01L23/49541 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/03

    摘要： A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces.

    摘要翻译： 芯片封装结构包括其上具有粘合剂层的芯片放置的框架; 芯片包括在其上的活性表面上的多个焊盘，并且设置在粘合剂层上; 封装结构被覆盖在芯片放置的框架的四边周围，并且封装结构的高度大于芯片的高度; 多个图案化的金属迹线电连接到多个焊盘，另一端延伸以覆盖封装结构的表面; 图案化的保护层被覆盖在图案化的金属迹线上，并且图案化的金属迹线的另一端被暴露; 在图案化的金属迹线的延伸表面上形成多个图案化的UBM层; 并且多个导电元件形成在图案化的UBM层上并且电连接到图案化金属迹线的暴露部分的一端。