公开(公告)号：US20100178734A1

公开(公告)日：2010-07-15

申请号：US12189165

申请日：2008-08-10

Applicant: Hung-Tsun LIN

Inventor： Hung-Tsun LIN

IPC: H01L21/60

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10165 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages. Furthermore, the manufacturing processes include two half-etching steps to form the half-etched leadframe where a second half-etching step is performed after forming the encapsulant and before forming the electroplated layer.

Abstract translation: 公开了一种具有嵌入密封剂中的电镀层的无引线半导体封装及其制造工艺。 封装主要包括半蚀刻引线框架，芯片，密封剂和电镀层。 半蚀刻引线框架具有多个引线和与引线整体连接的多个外焊盘。 密封剂封装芯片和引线，并且具有到达外部焊盘的多个空腔，以在外部焊盘上形成电镀层并嵌入空腔中。 因此，在降低成本和较高散热的优点下，可以更换常规基板及其用于BGA（球栅阵列）或LGA（Land Grid Array）封装的焊接掩模。 封装在密封剂中的引线具有更好的接合强度，并且嵌入密封剂中的电镀层在运输，处理或存储半导体封装期间不会被损坏。 此外，制造工艺包括形成半蚀刻引线框架的两个半蚀刻步骤，其中在形成密封剂之后和形成电镀层之前执行第二半蚀刻步骤。

公开(公告)号：US20090189296A1

公开(公告)日：2009-07-30

申请号：US12275172

申请日：2008-11-20

Applicant: Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

Inventor： Cheng-Ting Wu ,  Hung-Tsun Lin ,  Yu-Ren Chen ,  Chun-Ying Lin

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/3114 ,  H01L23/49517 ,  H01L23/49822 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

Abstract translation: 提供了一种倒装芯片四边形扁平无铅封装结构的制造方法。 首先在制造方法中设置具有多根引线的引线框架。 在引线框架上形成介电层，并使引线的顶表面和底表面露出。 在电介质层上形成包括多个焊盘的重分配层和连接焊盘和引线顶表面的多条导线。 形成阻焊层以覆盖再分布层，电介质层和引线，并露出焊盘的表面。 在阻焊层上形成粘接层。 提供具有多个凸块的芯片。 该芯片用粘合剂层粘附在阻焊层上，并且每个凸块与其中一个焊盘电连接。

公开(公告)号：US20090039533A1

公开(公告)日：2009-02-12

申请号：US12173920

申请日：2008-07-16

Applicant: Hung-Tsun Lin ,  Yu-Ren Chen

Inventor： Hung-Tsun Lin ,  Yu-Ren Chen

IPC: H01L23/12 ,  H01L21/58

CPC classification number: H01L23/13 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A packaging apparatus is disclosed having a substrate with an interior area and a peripheral area. The substrate is configured to have an integrated circuit chip bonded to an adhesion structure located substantially within the interior area of the substrate. The substrate is further configured to have the integrated circuit chip electrically coupled to either the interior area on a distal surface of the substrate or the peripheral area on a proximate side of the substrate through a conductive structure. The adhesion structure includes a bonding area configured to accept an adhesive layer formed between the integrated circuit chip and the interior area of the substrate, and at least one protrusion structure being formed substantially within the bonding area of the substrate and configured to define a gap between the integrated circuit chip and the interior area of the substrate.

Abstract translation: 公开了一种具有内部区域和周边区域的基板的包装装置。 衬底被配置为具有结合到基本上位于衬底的内部区域内的粘附结构的集成电路芯片。 衬底还被配置为使得集成电路芯片通过导电结构电耦合到衬底的远侧表面上的内部区域或衬底的近侧上的周边区域。 粘合结构包括：接合区域，其被配置为接纳在集成电路芯片和衬底的内部区域之间形成的粘合层;以及至少一个凸起结构，其基本上形成在衬底的接合区域内， 集成电路芯片和衬底的内部区域。

公开(公告)号：US20080099892A1

公开(公告)日：2008-05-01

申请号：US11882551

申请日：2007-08-02

Applicant: Yu-Ren Chen ,  Geng-Shin Shen ,  Hung-Tsun Lin

Inventor： Yu-Ren Chen ,  Geng-Shin Shen ,  Hung-Tsun Lin

IPC: H01L23/495

CPC classification number: H01L23/3121 ,  H01L23/49517 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Abstract translation: 一种具有引线框架的堆叠封装结构，具有汇流条，包括：引线框架，由相互排列成行的多个内部引线，多个外部引线和管芯焊盘组成，其中管芯焊盘设置在内部引线之间 并且与内引线垂直; 在所述内引线和所述管芯焊盘之间设置母线; 由多个芯片堆叠的偏移芯片堆叠结构，所述偏移芯片堆叠结构固定地连接到所述管芯焊盘的第一表面并电连接到所述内部引线; 以及覆盖偏移芯片堆叠结构的密封剂，内引线，管芯焊盘的第一表面和母线的上表面，裸片焊盘的第二表面和母线的下表面被暴露，并且外引线延伸 从密封剂出来。

公开(公告)号：US20070290301A1

公开(公告)日：2007-12-20

申请号：US11601752

申请日：2006-11-20

Applicant: Hung-Tsun Lin

Inventor： Hung-Tsun Lin

IPC: H01L23/552

CPC classification number: H01L24/85 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A multi-chip stacked package is revealed, primarily comprising a spacer pad and a plurality of leads of a lead frame, a first chip, a second chip, and an encapsulant. A plurality of first electrodes are formed on the active surface of the first chip below the spacer pad and are electrically connected to one surfaces of the leads. A plurality of second electrodes are formed on the active surface of the second chip above the spacer pad and are electrically connected to the same surfaces of the leads. The encapsulant encapsulates the spacer pad, parts of the leads, the first chip, and the second chip where the active surface of the first chip is attached to the bottom surface of the spacer pad and the back surface of the second chip to the top surface of the spacer pad. Moreover, the spacer pad does not cover the first electrodes of the first chip for wire-bonding to achieve multi-chip stacking with a reduced overall package thickness.

Abstract translation: 揭示了多芯片堆叠封装，主要包括间隔垫和引线框，第一芯片，第二芯片和密封剂的多个引线。 在间隔垫下方的第一芯片的有源表面上形成多个第一电极，并且电连接到引线的一个表面。 多个第二电极形成在间隔垫上方的第二芯片的有源表面上，并且电连接到引线的相同表面。 密封剂封装间隔垫，引线部分，第一芯片和第二芯片，其中第一芯片的有源表面附接到间隔垫的底表面和第二芯片的后表面到顶表面 的间隔垫。 此外，间隔垫不覆盖用于引线接合的第一芯片的第一电极，以实现减少整体封装厚度的多芯片堆叠。

公开(公告)号：US20070222040A1

公开(公告)日：2007-09-27

申请号：US11580309

申请日：2006-10-13

Applicant: Hung-Tsun Lin

Inventor： Hung-Tsun Lin

IPC: H01L23/495

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10165 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages. Furthermore, the manufacturing processes include two half-etching steps to form the half-etched leadframe where a second half-etching step is performed after forming the encapsulant and before forming the electroplated layer.

Abstract translation: 公开了一种具有嵌入密封剂中的电镀层的无引线半导体封装及其制造工艺。 封装主要包括半蚀刻引线框架，芯片，密封剂和电镀层。 半蚀刻引线框架具有多个引线和与引线整体连接的多个外焊盘。 密封剂封装芯片和引线，并且具有到达外部焊盘的多个空腔，以在外部焊盘上形成电镀层并嵌入空腔中。 因此，在降低成本和较高散热的优点下，可以更换常规基板及其用于BGA（球栅阵列）或LGA（Land Grid Array）封装的焊接掩模。 封装在密封剂中的引线具有更好的接合强度，并且嵌入密封剂中的电镀层在运输，处理或存储半导体封装期间不会被损坏。 此外，制造工艺包括形成半蚀刻引线框架的两个半蚀刻步骤，其中在形成密封剂之后和形成电镀层之前执行第二半蚀刻步骤。

公开(公告)号：US20070215995A1

公开(公告)日：2007-09-20

申请号：US11580310

申请日：2006-10-13

Applicant: Hung-Tsun Lin

Inventor： Hung-Tsun Lin

IPC: H01L23/495

CPC classification number: H01L23/3107 ,  H01L21/4828 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49541 ,  H01L24/48 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Manufacturing processes of a leadframe-based BGA package and a leadless leadframe implemented in the processes are disclosed. The leadless leadframe has a plurality of bottom leads and a plurality of top soldering pads formed in different layers. After encapsulation and before solder ball placement, a half-etching process is performed to remove the bottom leads to make the top soldering pads electrically isolated, exposed and embedded in the encapsulant for solder ball placement where the soldering area of the top soldering pads is defined without the need of solder mask(s) to solve the diffusion of solder balls on the leads during reflow. Moreover, mold flash can easily be detected and removed. The overall package cost can be reduced.

Abstract translation: 公开了在该方法中实现的基于引线框的BGA封装和无引线框架的制造工艺。 无引线框架具有多个底部引线和形成在不同层中的多个顶部焊盘。 在封装之后和焊球放置之前，进行半蚀刻工艺以去除底部引线，使顶部焊盘电隔离，暴露并嵌入密封剂中用于焊球放置，其中顶部焊盘的焊接区域被定义 而不需要焊接掩模来解决在回流期间焊球在引线上的扩散。 此外，可以容易地检测和去除模具闪光。 整体包装成本可以降低。

公开(公告)号：US07663246B2

公开(公告)日：2010-02-16

申请号：US11882551

申请日：2007-08-02

Applicant: Yu-Ren Chen ,  Geng-Shin Shen ,  Hung Tsun Lin

Inventor： Yu-Ren Chen ,  Geng-Shin Shen ,  Hung Tsun Lin

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L23/49517 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Abstract translation: 一种具有引线框架的堆叠封装结构，具有汇流条，包括：引线框架，由相互排列成行的多个内部引线，多个外部引线和管芯焊盘组成，其中管芯焊盘设置在内部引线之间 并且与内引线垂直; 在所述内引线和所述管芯焊盘之间设置母线; 由多个芯片堆叠的偏移芯片堆叠结构，所述偏移芯片堆叠结构固定地连接到所述管芯焊盘的第一表面并电连接到所述内部引线; 以及覆盖偏移芯片堆叠结构的密封剂，内引线，管芯焊盘的第一表面和母线的上表面，裸片焊盘的第二表面和母线的下表面被暴露，并且外引线延伸 从密封剂出来。

公开(公告)号：US07582953B2

公开(公告)日：2009-09-01

申请号：US11882820

申请日：2007-08-06

Applicant: Hung Tsun Lin

Inventor： Hung Tsun Lin

IPC: H01L23/48

CPC classification number: H01L23/49575 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of inner leads are divided into first inner leads and second inner leads, and the length of the first inner leads is greater than that of the second inner leads; and a plurality of semiconductor chip devices. The active surface of each chip faces upward and chips are misaligned to form offset stacked structure, wherein the semiconductor chip device stacked uppermost is fixedly connected under said first inner leads, and the plurality of semiconductor chip devices are electrically connected to the first inner leads and the second inner leads on the same side edge.

Abstract translation: 本发明提供了一种在堆叠芯片上具有引线框架的封装结构，包括：引线框架，由相互排列成行的多个外引线和由彼此面对的多个内引线组成， 多个线，其中所述多个内引线被分成第一内引线和第二内引线，并且所述第一内引线的长度大于所述第二内引线的长度; 和多个半导体芯片器件。 每个芯片的有源表面朝上并且芯片不对准以形成偏移堆叠结构，其中堆叠在最上面的半导体芯片器件固定地连接在所述第一内引线下方，并且多个半导体芯片器件电连接到第一内引线， 第二个内引线在同一侧边。

公开(公告)号：US20090087953A1

公开(公告)日：2009-04-02

申请号：US12153451

申请日：2008-05-19

Applicant: Hung-Tsun Lin

Inventor： Hung-Tsun Lin

IPC: H01L21/50

CPC classification number: H01L23/3107 ,  H01L21/4828 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49534 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10S438/94 ,  Y10S438/959 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract translation: 公开了一种基于引线框架的BGA封装的制造工艺。 为封装提供了具有上层和下层的无引线框架。 上层包括多个球垫，下层包括与球垫对准并连接的多个牺牲垫。 在上层或下层中形成多个引线以互连球垫或牺牲垫。 形成密封剂以在芯片附接和电连接之后嵌入球垫。 在制造过程中，在封装之后执行半蚀刻工艺以去除牺牲焊盘，以使球垫与密封剂电隔离并暴露于焊球放置处，其中限定了焊盘的焊接区域，而不需要焊接掩模 以解决在回流期间引线上的焊球渗漏或不期望的斑点的问题。 此外，可以容易地检测和去除模具闪光。