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    Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit
    1.
    发明授权
    Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit 失效
    使用公共校准基准和校准电路校准半导体器件的方法

    公开(公告)号：US06958613B2

    公开(公告)日：2005-10-25

    申请号：US10675492

    申请日：2003-09-30

    申请人： Georg Braun ,  Hermann Ruckerbauer ,  Simon Muff

    发明人： Georg Braun ,  Hermann Ruckerbauer ,  Simon Muff

    IPC分类号： G01R35/00 ,  G06F11/24 ,  G06F11/27 ,  G06F13/38 ,  G11C7/10 ,  G11C29/02 ,  H04L7/04

    CPC分类号： G11C29/022 ,  G06F11/24 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

    摘要： Interface parameters for a plurality of semiconductor devices, particularly parameters for output drivers (i.e. on chip driver) and terminations (i.e. on die termination) for double data rate dynamic random access memories, are aligned using a calibration reference which is common to the semiconductor devices and is connected to calibration connections on the semiconductor devices. The semiconductor devices are calibrated in succession, in each case individually, and the calibration connection on the respective semiconductor device which is currently performing calibration is connected to an internal calibration unit by an internal switching unit in the process, and the calibration connections on all other semiconductor devices are terminated to a high impedance internally.

    摘要翻译： 用于双数据速率动态随机存取存储器的多个半导体器件的接口参数，特别是用于输出驱动器（即片上驱动器）的参数和终端（即，芯片端接）的参数使用半导体器件公共的校准参考 并连接到半导体器件上的校准连接。 半导体器件在每种情况下分别校准，并且当前正在执行校准的相应半导体器件上的校准连接通过该过程中的内部切换单元连接到内部校准单元，并且所有其他校准连接 半导体器件在内部被端接到高阻抗。

    Re-driving CAwD and rD signal lines
    2.
    发明授权
    Re-driving CAwD and rD signal lines 失效
    重新启动CAwD和rD信号线

    公开(公告)号：US07414917B2

    公开(公告)日：2008-08-19

    申请号：US11192335

    申请日：2005-07-29

    申请人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    发明人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    IPC分类号： G11C8/00

    CPC分类号： G11C5/04 ,  G11C5/06 ,  H05K1/142

    摘要： Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.

    摘要翻译： 本文描述了使用其的半导体存储器模块和半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

    Semiconductor memory module and system
    6.
    发明申请
    Semiconductor memory module and system 失效
    半导体存储器模块和系统

    公开(公告)号：US20070025131A1

    公开(公告)日：2007-02-01

    申请号：US11192335

    申请日：2005-07-29

    申请人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    发明人： Hermann Ruckerbauer ,  Simon Muff ,  Christian Weiss ,  Peter Gregorius

    IPC分类号： G11C5/06

    CPC分类号： G11C5/04 ,  G11C5/06 ,  H05K1/142

    摘要： The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.

    摘要翻译： 本发明包括半导体存储器模块和使用其的半导体存储器系统。 这些模块将常规DIMM分成一系列独立的较小内存模块。 每个存储器模块包括布置在衬底上的至少一个半导体存储器芯片; CAwD信号输入线，以第一预定行号排列在基板上，并将半导体存储器芯片之一连接到基板上的CAwD输入信号引脚; 和rD信号输出线，以第二预定行号排列在基板上，并将一个或最后一个半导体存储器连接到基板的第二数量的rD输出信号引脚。 在包括半导体存储器模块的半导体存储器系统中，每个存储器模块通过CAwD信号输入线和rD信号输出线分别以点对点的方式连接到存储器控制器。

    Circuit system
    7.
    发明申请
    Circuit system 审中-公开
    电路系统

    公开(公告)号：US20060248260A1

    公开(公告)日：2006-11-02

    申请号：US11392217

    申请日：2006-03-29

    申请人： Maksim Kuzmenka ,  Simon Muff ,  Hermann Ruckerbauer

    发明人： Maksim Kuzmenka ,  Simon Muff ,  Hermann Ruckerbauer

    IPC分类号： G06F12/02

    CPC分类号： H03K19/018514 ,  H03K19/0175 ,  H03K19/01812

    摘要： A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.

    摘要翻译： 电路系统包括用于通过差分控制信号控制第一和第二存储器单元的装置。 差分控制信号包括第一控制信号和第二控制信号，其被反转到第一控制信号。 此外，电路系统包括差分控制信号线，其包括用于路由第一控制信号的第一信号线和用于路由第二控制信号的第二信号线。 第一开关单元经由第一信号线连接，第二电路单元经由第二信号线连接到控制装置。

    Integrated circuit
    8.
    发明授权
    Integrated circuit 失效
    集成电路

    公开(公告)号：US06911732B2

    公开(公告)日：2005-06-28

    申请号：US10137511

    申请日：2002-04-30

    申请人： Simon Muff ,  Martin Gall ,  Andre Schaefer ,  Georg Braun

    发明人： Simon Muff ,  Martin Gall ,  Andre Schaefer ,  Georg Braun

    IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/50 ,  H01L23/66

    CPC分类号： H01L23/66 ,  H01L2224/49175 ,  H01L2924/15173 ,  H01L2924/30107 ,  H01L2924/00

    摘要： An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.

    摘要翻译： 一种集成在壳体中的集成电路，其具有装配到壳体的连接销，用于将外壳连接到外部电路的信号线，每个连接引脚通过相关布线连接到集成在外壳中的电路的接触焊盘， 在外部电路和集成电路之间交换信号，其中最小化相关布线的线路长度，要连接到用于高频信号的信号线的连接引脚被集中地安装到壳体。

    Encasing arrangement for a semiconductor component
    10.
    发明授权
    Encasing arrangement for a semiconductor component 有权
    半导体元件的封装结构

    公开(公告)号：US07208827B2

    公开(公告)日：2007-04-24

    申请号：US10149892

    申请日：2000-12-13

    申请人： Christian Hauser ,  Simon Muff ,  Jens Pohl ,  Friedrich Wanninger

    发明人： Christian Hauser ,  Simon Muff ,  Jens Pohl ,  Friedrich Wanninger

    IPC分类号： H01L23/22 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/3677 ,  H01L2224/27013 ,  H01L2224/83051 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025

    摘要： A semiconductor component package configuration includes a semiconductor chip mounted to a printed circuit board, and a substrate arranged between the semiconductor chip and the printed circuit board. The substrate is for routing the wiring terminals of the semiconductor chip to the printed circuit board. The substrate is connected to the printed circuit board by solder joints. A filler between the semiconductor chip and the substrate mechanically isolates the semiconductor chip and the solder joints. A metal layer, which is connected to solder joints, is applied to the substrate. At least one molded element of heat-dissipating material is applied to the metal layer and is connected in a heat-conducting manner to the metal layer. This provides the package configuration with an improved capability of conducting the lost power that is dissipated from the installed semiconductor chip, and the desired mechanical properties of the package arrangement are retained.

    摘要翻译： 半导体部件封装构造包括安装到印刷电路板的半导体芯片和布置在半导体芯片和印刷电路板之间的基板。 基板用于将半导体芯片的布线端子布线到印刷电路板。 基板通过焊点连接到印刷电路板。 半导体芯片和基板之间的填充物机械地隔离半导体芯片和焊点。 将连接到焊接点的金属层施加到基板。 将至少一个散热材料的模制元件施加到金属层，并以导热方式连接到金属层。 这提供了封装配置，其具有改进的能够从所安装的半导体芯片散发的损失功率的能力，并且保持了封装布置的期望的机械特性。