公开(公告)号：US5148533A

公开(公告)日：1992-09-15

申请号：US294534

申请日：1989-01-05

申请人： Thomas F. Joyce ,  Robert C. Miller ,  Marc C. Vogt

发明人： Thomas F. Joyce ,  Robert C. Miller ,  Marc C. Vogt

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory. The monitor unit, in response to signals applied to the system bus, identifies operations that can compromise the integrity of signals stored in the associated data processing unit. The monitor unit accesses the appropriate duplicate directory to determine if the address of a compromised data group validly exists in the duplicate directory. When an address is stored in the duplicate directory along with a valid signal, the valid signal is removed from both the cache directory and the duplicate directory.

摘要翻译： 在具有通过异步系统总线连接的多个紧密耦合的数据处理单元的数据处理系统中，描述了用于维持存储在指令高速缓存单元和执行高速缓存单元中的数据组的一致性的装置和相关联的方法。 该装置包括作为总线接口单元的一部分的监视器单元和将每个相关联的数据处理单元耦合到系统总线的总线接口单元。 监视器单元接收施加到系统总线的信号，识别在存储器单元和数据处理单元之间传送的数据组，包括源自监视器单元是组件的总线接口单元的那些数据组。 总线接口单元包括复制指令高速缓存单元目录和执行高速缓存单元目录的内容的目录。 监视器单元响应于施加到系统总线的信号来识别可能危及存储在相关联的数据处理单元中的信号的完整性的操作。 监视器单元访问适当的重复目录，以确定受损数据组的地址是否有效存在于重复目录中。 当地址与有效信号一起存储在重复目录中时，有效信号将从缓存目录和重复目录中移除。

公开(公告)号：US5193181A

公开(公告)日：1993-03-09

申请号：US593458

申请日：1990-10-05

申请人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

发明人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

IPC分类号： G06F11/00 ,  G06F11/22

CPC分类号： G06F11/0793 ,  G06F11/0724 ,  G06F11/0766 ,  G06F11/004 ,  G06F11/2205

摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

公开(公告)号：US6125436A

公开(公告)日：2000-09-26

申请号：US855810

申请日：1997-05-12

申请人： James F. Bertone ,  Bruno DiPlacido, Jr. ,  Thomas F. Joyce ,  Martin Massucci ,  Lance J. McNally ,  Thomas L. Murray, Jr. ,  Chester M. Nibby, Jr. ,  Michelle A. Pence ,  Marc Sanfacon ,  Jian-Kuo Shen ,  Jeffrey S. Somers ,  G. Lewis Steiner

发明人： James F. Bertone ,  Bruno DiPlacido, Jr. ,  Thomas F. Joyce ,  Martin Massucci ,  Lance J. McNally ,  Thomas L. Murray, Jr. ,  Chester M. Nibby, Jr. ,  Michelle A. Pence ,  Marc Sanfacon ,  Jian-Kuo Shen ,  Jeffrey S. Somers ,  G. Lewis Steiner

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/368 ,  G06F12/00

CPC分类号： G06F13/1657 ,  G06F12/0831 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/368

摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

摘要翻译： 具有统一环境和分布式系统功能的对称多处理系统为系统中的所有功能单元提供统一的地址空间，同时在系统的功能单元上分配各种系统功能的执行，每个功能单元承担其自身方面的责任 操作。 此外，该系统提供改进的系统总线操作，用于从存储器传输数据。

公开(公告)号：US5283870A

公开(公告)日：1994-02-01

申请号：US771296

申请日：1991-10-04

申请人： Thomas F. Joyce ,  James W. Keeley

发明人： Thomas F. Joyce ,  James W. Keeley

IPC分类号： G06F9/46 ,  G06F15/167 ,  G06F13/14

CPC分类号： G06F9/524 ,  G06F15/167

摘要： A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.

摘要翻译： 多处理器系统包括许多系统处理器，其紧密耦合到系统总线以共享主或系统存储器以及还紧密耦合到系统总线的多个板载存储器处理器。 每个处理器都有一个高性能微处理器，通过微处理器的本地总线紧密耦合到板载或本地存储器。 使用内存锁定协议访问系统内存，而本地内存可通过总线锁定协议访问。 每个板上存储器处理器包括锁机构，其能够处理针对其本地存储器的存储器锁定命令，该存储器锁定命令经由系统总线从任何其他处理器接收并用于向系统存储器发出存储器锁定命令。

公开(公告)号：US4942547A

公开(公告)日：1990-07-17

申请号：US131246

申请日：1987-12-07

申请人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen ,  Michel M. Raguin

发明人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen ,  Michel M. Raguin

IPC分类号： G06F9/38

CPC分类号： G06F9/3885

摘要： A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.

摘要翻译： 数据处理系统包括商业指令处理器，科学指令处理器和集成到单个半导体逻辑元件中的基本指令处理器的功能。

公开(公告)号：US4295203A

公开(公告)日：1981-10-13

申请号：US92907

申请日：1979-11-09

申请人： Thomas F. Joyce

发明人： Thomas F. Joyce

IPC分类号： G06F7/57 ,  G06F7/48

CPC分类号： G06F7/483 ,  G06F7/49936 ,  G06F7/49947

摘要： If the firmware calls for an operand rounding operation, apparatus in the Scientific Instruction Processor (SIP) tests the bit to the right of the low order bit of the normalized operand to determine if a rounding cycle is required. If the operand requires a normalization cycle or a mantissa overflow correction cycle, the rounding operation is performed in those cycles.

摘要翻译： 如果固件要求操作数舍入操作，则科学指令处理器（SIP）中的设备将测试归一化操作数的低位位右侧的位，以确定是否需要舍入周期。 如果操作数需要归一化周期或尾数溢出校正周期，则在这些周期中执行舍入操作。

公开(公告)号：US4157587A

公开(公告)日：1979-06-05

申请号：US863095

申请日：1977-12-22

申请人： Thomas F. Joyce ,  Thomas O. Holtey

发明人： Thomas F. Joyce ,  Thomas O. Holtey

IPC分类号： F02B75/02 ,  G06F12/08 ,  G06F12/12 ,  G06F9/00 ,  G06F13/00 ,  G11C9/00 ,  G11C9/06

CPC分类号： G06F12/123 ,  G06F12/0862 ,  F02B2075/027 ,  G06F2212/6022

摘要： A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.

摘要翻译： 数据处理系统包括多个系统单元，它们都共同连接到系统总线。 系统单元包括中央处理器（CPU），存储器系统和高速缓冲器或缓存系统。 缓存系统是面向字的，包括一个目录，一个数据缓冲器和相关的控制逻辑。 CPU通过将请求的数据字的主存储器地址发送到高速缓存系统来请求数据字。 如果高速缓存不具有信息，则高速缓存中的装置请求来自主存储器的信息，此外，该装置从连续更高的地址请求附加信息。 如果主存储器正忙，则缓存器具有要求较少字的设备。

公开(公告)号：US5809340A

公开(公告)日：1998-09-15

申请号：US909745

申请日：1997-08-12

申请人： James F. Bertone ,  Bruno DiPlacido, Jr. ,  Thomas F. Joyce ,  Martin Massucci ,  Lance J. McNally ,  Thomas L. Murray, Jr. ,  Chester M. Nibby, Jr. ,  Michelle A. Pence ,  Marc Sanfacon ,  Jian-Kuo Shen ,  Jeffrey S. Somers ,  G. Lewis Steiner ,  William S. Wu ,  Norman J. Rasmussen ,  Suresh K. Marisetty ,  Puthiya K. Nizar

发明人： James F. Bertone ,  Bruno DiPlacido, Jr. ,  Thomas F. Joyce ,  Martin Massucci ,  Lance J. McNally ,  Thomas L. Murray, Jr. ,  Chester M. Nibby, Jr. ,  Michelle A. Pence ,  Marc Sanfacon ,  Jian-Kuo Shen ,  Jeffrey S. Somers ,  G. Lewis Steiner ,  William S. Wu ,  Norman J. Rasmussen ,  Suresh K. Marisetty ,  Puthiya K. Nizar

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/368

CPC分类号： G06F13/1694 ,  G06F12/0831 ,  G06F13/1657 ,  G06F13/1689 ,  G06F13/368

摘要： Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

摘要翻译： 基于第一和第二定时控制值，计算机系统中的定时计算器装置被用于自适应地生成适合多种存储器类型的存取信号，其中第一定时控制值表示特定于并限于开始的信息 并且其中所述第二定时控制值表示表示其他定时事件的信息。 也就是说，本发明的状态机需要与其他定时值分开的独特的启动控制值，用于计算适当的存储器访问参数。

公开(公告)号：US5053951A

公开(公告)日：1991-10-01

申请号：US331054

申请日：1989-03-28

申请人： Eugene Nusinov ,  Thomas F. Joyce

发明人： Eugene Nusinov ,  Thomas F. Joyce

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/1036 ,  G06F12/145 ,  Y02B60/1225

摘要： A segment descriptor unit (SDU) includes a divided random access memory (RAM), a content addressable memory (CAM) and decoder circuits interconnected for performing dynamic and static address translation operations within a minimum of chip area and power. The CAM is arranged to store a number of entries which include segment number and validity information associated with a corresponding number of segment descriptors. The RAM contains locations allocated for storing segment descriptor words (SDW's) and working data. Each SDW is logically divided into two fields, a static translation word (STW) field containing all of the bits required for performing a static address translation operation and an access control word (ACW) field containing all of the bits required for verifying compliance with system security. The bits of each STW and ACW are stored in alternate bit positions of the SDW locations. Each pair of RAM bit locations couple to a common read/write amplifier and multiplexer circuit. Through the use of microinstruction commands coded to specify different address translation functions, the STW and ACW fields selected by the CAM are read out from RAM during different intervals for carrying out the steps of those operations.

摘要翻译： 段描述符单元（SDU）包括分离的随机存取存储器（RAM），内容可寻址存储器（CAM）和互连的解码器电路，用于在最小的芯片面积和功率内执行动态和静态地址转换操作。 CAM被设置为存储多个条目，其包括与相应数量的段描述符相关联的段号和有效性信息。 RAM包含分配用于存储段描述符字（SDW）和工作数据的位置。 每个SDW在逻辑上分为两个字段，一个包含执行静态地址转换操作所需的所有位的静态转换字（STW）字段和包含用于验证系统符合性所需的所有位的访问控制字（ACW）字段 安全。 每个STW和ACW的位被存储在SDW位置的交替位位置。 每对RAM位位置耦合到公共读/写放大器和多路复用器电路。 通过使用编码的微指令命令来指定不同的地址转换功能，在不同间隔期间，从RAM中选择的STW和ACW字段从RAM中读出，以执行这些操作的步骤。

公开(公告)号：US4813002A

公开(公告)日：1989-03-14

申请号：US887768

申请日：1986-07-21

申请人： Thomas F. Joyce ,  Eugene Nusinov ,  Richard P. Brown

发明人： Thomas F. Joyce ,  Eugene Nusinov ,  Richard P. Brown

IPC分类号： G06F12/10 ,  G11C15/04 ,  G11C15/00

CPC分类号： G06F12/1027 ,  G11C15/04

摘要： A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time then required for a single CAM memory. The results are logically combined with in the RAM which, in response to a match condition, delivers the results of the translation as an output.

摘要翻译： 翻译器被组织成包括至少一对内容可寻址存储器（CAM），每个存储器可用于存储要翻译的每个字的总位数的不同部分。 每个CAM的输出在逻辑上组合在一个多输入随机存取存储器（RAM）中。 两个CAM被同时询问并且将输入字和CAM内容的字部分与RAM相比较的结果，在单个CAM存储器所需要的时间上要少得多。 结果在逻辑上与RAM相结合，RAM响应于匹配条件将转换的结果传递为输出。