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    Non-volatile memory with sidewall channels and raised source/drain regions
    3.
    发明授权
    Non-volatile memory with sidewall channels and raised source/drain regions 有权
    具有侧壁通道和升高的源极/漏极区域的非易失性存储器

    公开(公告)号：US07915664B2

    公开(公告)日：2011-03-29

    申请号：US12105242

    申请日：2008-04-17

    申请人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    发明人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    IPC分类号： H01L29/788

    CPC分类号： G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

    摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

    摘要翻译： 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

    NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS
    4.
    发明申请
    NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 有权
    非易失性存储器，带有通道和扩展源/漏区

    公开(公告)号：US20090261398A1

    公开(公告)日：2009-10-22

    申请号：US12105242

    申请日：2008-04-17

    申请人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    发明人： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    IPC分类号： H01L29/788

    CPC分类号： G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

    摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

    摘要翻译： 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

    Method for forming self-aligned dielectric cap above floating gate
    5.
    发明授权
    Method for forming self-aligned dielectric cap above floating gate 有权
    在浮动栅上形成自对准电介质盖的方法

    公开(公告)号：US08207036B2

    公开(公告)日：2012-06-26

    申请号：US12242857

    申请日：2008-09-30

    申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

    发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

    摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.

    摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。

    METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE
    8.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE 有权
    在浮动门上形成自对准电介质盖的方法

    公开(公告)号：US20100081267A1

    公开(公告)日：2010-04-01

    申请号：US12242857

    申请日：2008-09-30

    申请人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

    发明人： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  Henry Chien ,  James K. Kai

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/513 ,  H01L29/7881

    摘要： A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.

    摘要翻译： 一种用于制造非易失性存储元件的方法。 该方法包括在衬底上形成多晶硅浮栅材料层，并在多晶硅浮栅材料的表面形成一层氮化物。 浮栅由多晶硅浮栅材料形成。 各个绝缘盖由氮化物形成，使得每个单独的氮化物介电帽与多个浮动栅之一自对准。 在电介质盖的表面和浮动栅极的侧面上形成栅极间介电层。 然后，栅极介电层与控制栅极与浮动栅极分离形成控制栅极。 可以使用SPA（槽平面天线）氮化形成氮化物层。 可以在蚀刻多晶硅浮栅材料之前或之后形成氮化物层以形成浮栅。

    Methods of forming NAND flash memory with fixed charge
    9.
    发明授权
    Methods of forming NAND flash memory with fixed charge 有权
    用固定电荷形成NAND闪存的方法

    公开(公告)号：US08030160B2

    公开(公告)日：2011-10-04

    申请号：US12729874

    申请日：2010-03-23

    申请人： Takashi Orimoto ,  George Matamis ,  Henry Chien ,  James Kai

    发明人： Takashi Orimoto ,  George Matamis ,  Henry Chien ,  James Kai

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.

    摘要翻译： 一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。 这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。 固定电荷层也可以在源极/漏极区域上延伸。

    Methods Of Forming Integrated Circuit Devices Using Composite Spacer Structures
    10.
    发明申请
    Methods Of Forming Integrated Circuit Devices Using Composite Spacer Structures 有权
    使用复合间隔结构形成集成电路器件的方法

    公开(公告)号：US20080171406A1

    公开(公告)日：2008-07-17

    申请号：US12014689

    申请日：2008-01-15

    申请人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

    发明人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

    摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

    摘要翻译： 使用复合间隔物形成工艺提供制造集成电路器件的方法。 当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。 复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。 该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。 此外，等于线和空间大小小于最小特征尺寸。 在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。 当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。