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公开(公告)号：US07639535B2
公开(公告)日：2009-12-29
申请号：US11601124
申请日：2006-11-17
IPC分类号： G11C11/34
CPC分类号： G11C29/50 , G11C16/04 , G11C29/12 , G11C29/12005 , G11C29/4401 , G11C29/70 , G11C2029/4002 , G11C2029/5006
摘要： A non-volatile memory may have memory portions, such as blocks or other granularities of units of memory, which may fail in actual use. These defective portions can be replaced with other portions which may, in some cases, be of corresponding size. In some embodiments, defects may be detected using a current sensor which detects the current drawn in actual operation. If an excessive current is drawn, this may be detected, the defective unit deactivated, and a replacement provided in its stead. This may result in the repair of a defect with little inconvenience to the user in some embodiments.
摘要翻译： 非易失性存储器可以具有诸如块或存储器单位的其他粒度的存储器部分，其可能在实际使用中失败。 这些缺陷部分可以用其他部分替代，在某些情况下，这些部分可能具有相应的尺寸。 在一些实施例中，可以使用检测在实际操作中绘制的电流的电流传感器来检测缺陷。 如果画出过大的电流，则可能会检测到这种情况，故障单元会被停用，并且替换为替代。 这在一些实施例中可能导致对用户的少量不便的修复。
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公开(公告)号：US20080117681A1
公开(公告)日：2008-05-22
申请号：US11601124
申请日：2006-11-17
CPC分类号： G11C29/50 , G11C16/04 , G11C29/12 , G11C29/12005 , G11C29/4401 , G11C29/70 , G11C2029/4002 , G11C2029/5006
摘要： A non-volatile memory may have memory portions, such as blocks or other granularities of units of memory, which may fail in actual use. These defective portions can be replaced with other portions which may, in some cases, be of corresponding size. In some embodiments, defects may be detected using a current sensor which detects the current drawn in actual operation. If an excessive current is drawn, this may be detected, the defective unit deactivated, and a replacement provided in its stead. This may result in the repair of a defect with little inconvenience to the user in some embodiments.
摘要翻译： 非易失性存储器可以具有诸如块或存储器单位的其他粒度的存储器部分，其可能在实际使用中失败。 这些缺陷部分可以用其他部分替代，在某些情况下，这些部分可能具有相应的尺寸。 在一些实施例中，可以使用检测在实际操作中绘制的电流的电流传感器来检测缺陷。 如果画出过大的电流，则可能会检测到这种情况，故障单元会被停用，并且替换为替代。 这在一些实施例中可能导致对用户的少量不便的修复。
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公开(公告)号：US08804449B2
公开(公告)日：2014-08-12
申请号：US13605538
申请日：2012-09-06
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/14 , G11C8/08 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/3427
摘要： An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.
摘要翻译： 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。
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公开(公告)号：US20140064010A1
公开(公告)日：2014-03-06
申请号：US13605538
申请日：2012-09-06
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/14 , G11C8/08 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/3427
摘要： An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.
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公开(公告)号：US20130043889A1
公开(公告)日：2013-02-21
申请号：US13210264
申请日：2011-08-15
IPC分类号： G01R27/26
CPC分类号： G01R31/028 , G01R31/024 , G01R31/025 , G11C29/02 , G11C29/025 , G11C29/50016 , G11C2029/5006
摘要： Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An example apparatus includes a leakage detection circuit configured to be coupled to a capacitance block. The leakage detection circuit is configured to determine whether a leakage current of a capacitance of the capacitance block exceeds a current limit and is further configured to provide an output indicative of a status of the capacitance. A detection controller is coupled to the leakage detection circuit and a register, and the detection controller is configured to store data in the register indicative of the status of the capacitance based at least in part on the signal from the leakage detection circuit.
摘要翻译： 描述用于评估电容的漏电流的装置和方法。 具有过大漏电流的电容可能会被禁止使用。 示例性装置包括被配置为耦合到电容块的泄漏检测电路。 泄漏检测电路被配置为确定电容块的电容的漏电流是否超过电流限制，并且还被配置为提供指示电容状态的输出。 检测控制器耦合到泄漏检测电路和寄存器，并且检测控制器被配置为至少部分地基于来自泄漏检测电路的信号将数据存储在指示电容状态的寄存器中。
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公开(公告)号：US20130272073A1
公开(公告)日：2013-10-17
申请号：US13443913
申请日：2012-04-11
申请人： Nicholas Hendrickson
发明人： Nicholas Hendrickson
摘要： Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.
摘要翻译： 公开了存储器装置中的命令信号管理方法和电路。 选择性地传递和阻止命令信号以在存储器件内实现安全的操作特性。 在至少一个实施例中，命令信号管理电路被配置为在正在执行存储器件操作的同时选择性地阻止命令信号。 在至少另一个实施例中，一个或多个命令阻塞电路被配置为在存储器件中正在执行存储器件操作时选择性地传递和阻止由耦合到存储器件的存储器访问器件产生的一个或多个命令信号。
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7.发明申请BLOCK-ROW DECODERS, MEMORY BLOCK-ROW DECODERS, MEMORIES, METHODS FOR DESELECTING A DECODER OF A MEMORY AND METHODS OF SELECTING A BLOCK OF MEMORY 有权块式解码器，存储器块解码器，存储器，用于描述存储器的解码器的方法和选择存储器块的方法公开(公告)号：US20120327735A1
公开(公告)日：2012-12-27
申请号：US13168699
申请日：2011-06-24
申请人： Nicholas Hendrickson
发明人： Nicholas Hendrickson
摘要： Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.
摘要翻译： 公开了块行解码器，存储器块行解码器，存储器，用于取消存储器解码器的方法和选择存储器块的方法。 示例性存储器块行解码器包括多个块行解码器，每个块行解码器具有解码器开关树。 每个块行解码器被配置为在块排解码器被取消选择的同时以第一电压偏置解码器开关树的块选择开关，并且还被配置为偏置解码器开关树的解码器开关，其耦合到块选择开关 在块排解码器被取消选择时具有第二电压，第二电压小于第一电压。 取消选择存储器的解码器的示例方法包括：在解码器被取消选择的同时，从解码器开关树的至少两个不同级别提供具有不同电压的解码器信号到解码器开关。
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公开(公告)号：US09159383B2
公开(公告)日：2015-10-13
申请号：US13443913
申请日：2012-04-11
申请人： Nicholas Hendrickson
发明人： Nicholas Hendrickson
摘要： Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.
摘要翻译： 公开了存储器装置中的命令信号管理方法和电路。 选择性地传递和阻止命令信号以在存储器件内实现安全的操作特性。 在至少一个实施例中，命令信号管理电路被配置为在正在执行存储器件操作的同时选择性地阻止命令信号。 在至少另一个实施例中，一个或多个命令阻塞电路被配置为在存储器件中正在执行存储器件操作时选择性地传递和阻止由耦合到存储器件的存储器访问器件产生的一个或多个命令信号。
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公开(公告)号：US09007822B2
公开(公告)日：2015-04-14
申请号：US13616545
申请日：2012-09-14
申请人： Nicholas Hendrickson
发明人： Nicholas Hendrickson
CPC分类号： G11C8/10 , G11C7/00 , G11C11/00 , G11C11/4087 , G11C11/4091 , G11C13/0026 , G11C16/06 , G11C16/08 , G11C16/24 , G11C16/26
摘要： Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.
摘要翻译： 公开了存储器件中的解码和解码器电路。 当存储器件中执行存储器件操作时，阵列线偏置或浮动。 在至少一个实施例中，解码器电路包括用于在执行特定存储器件操作时将阵列线或浮动阵列线偏置在存储器件中的互补器件。
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公开(公告)号：US08625345B2
公开(公告)日：2014-01-07
申请号：US13191836
申请日：2011-07-27
申请人： Nicholas Hendrickson
发明人： Nicholas Hendrickson
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/1033 , G11C7/1036 , G11C7/1039 , G11C7/106 , G11C11/5642 , G11C16/0458 , G11C16/0483 , G11C2207/2272 , G11C2211/5642
摘要： Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.
摘要翻译： 公开了操作存储器件的装置和方法。 在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器件传送，同时继续确定相同存储器单元的数据状态的剩余部分。 在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并且在存储器单元经历额外的检测相位时传送，以确定存储器单元的数据状态的附加部分。
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