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61 条记录 (耗时 0.031 秒)

    High impedance reference voltage distribution
    7.
    发明授权
    High impedance reference voltage distribution 有权
    高阻参考电压分布

    公开(公告)号：US07903478B1

    公开(公告)日：2011-03-08

    申请号：US12355466

    申请日：2009-01-16

    申请人： Marco Sforzin ,  Emanuele Confalonieri

    发明人： Marco Sforzin ,  Emanuele Confalonieri

    IPC分类号： G11C7/00

    CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C7/14

    摘要： A sense amplifier may be used to measure voltages and/or currents that represent logic levels stored in memory cells of memory devices. Accuracy and stability of such measurements may be improved by selective switching to isolate sense amplifiers from other portions of a circuit.

    摘要翻译： 读出放大器可用于测量表示存储在存储器件的存储器单元中的逻辑电平的电压和/或电流。 这种测量的精度和稳定性可以通过选择性地切换以将读出放大器与电路的其它部分隔离来提高。

    Method of managing a memory device employing three-level cells
    8.
    发明授权
    Method of managing a memory device employing three-level cells 有权
    管理使用三电平单元的存储器件的方法

    公开(公告)号：US07782665B2

    公开(公告)日：2010-08-24

    申请号：US12039268

    申请日：2008-02-28

    申请人： Paolo Turbanti ,  Carla Giuseppina Poidomani ,  Emanuele Confalonieri ,  Luigi Bettini

    发明人： Paolo Turbanti ,  Carla Giuseppina Poidomani ,  Emanuele Confalonieri ,  Luigi Bettini

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3436

    摘要： A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells.

    摘要翻译： 一种管理具有奇异寻址的三电平单元的多电平存储器件的方法包括通过根据编码方案将它们编码在相应的三进制字符串中来存储三位字符串，并将三个字符串中的每一个写入相应的一对三电平 细胞。 通过读取写在相应的三电平单元对中的各个三进制字符串来读取三位字符串，并根据编码方案对相应的三位串中的每个读取三进制串进行解码。 属于相同初始串和两个初始相邻串中的至少一个的一对相邻位通过识别对要编程的三电平单元的对来编程，所述三电平单元对三位串进行编程，并对每一对三电平进行编程 细胞。

    Memory device
    9.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US07352645B2

    公开(公告)日：2008-04-01

    申请号：US11250176

    申请日：2005-10-13

    申请人： Marco Sforzin ,  Emanuele Confalonieri ,  Nicola Del Gatto ,  Carla Giuseppina Poidomani

    发明人： Marco Sforzin ,  Emanuele Confalonieri ,  Nicola Del Gatto ,  Carla Giuseppina Poidomani

    IPC分类号： G11C7/00

    CPC分类号： G11C16/24 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    摘要： A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

    摘要翻译： 提供半导体存储器件。 半导体存储器件包括具有多个存储单元的存储器矩阵，存储器单元根据多个行排列，多个列和多个位线，每个位线与所述多个的至少一个相应的列相关联。 半导体存储器件还包括位线选择结构，用于选择所述位线中的至少一个和钳位电路结构，该钳位电路结构适于在一段时间内将与选定位线相邻且电容耦合的非选定位线的规定电压钳位 读操作。

    Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same
    10.
    发明授权
    Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same 有权
    具有输出信号切换噪声降低的非易失性存储器的输出缓冲器和包括该缓冲器的非易失性存储器

    公开(公告)号：US06788586B2

    公开(公告)日：2004-09-07

    申请号：US10161053

    申请日：2002-05-30

    申请人： Emanuele Confalonieri ,  Antonino Geraci ,  Marco Sforzin ,  Lorenzo Bedarida

    发明人： Emanuele Confalonieri ,  Antonino Geraci ,  Marco Sforzin ,  Lorenzo Bedarida

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1051

    摘要： Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

    摘要翻译： 这里描述的是一个输出缓冲器，它包括一个由上拉晶体管和一个下拉晶体管形成的输出级，它们串联连接在一个设在电源电位的电源线和一个设在地电位的地线之间， 中间节点连接到输出缓冲区的输出。 输出缓冲器还包括布置在输出缓冲器的输出端和上拉晶体管之间的单向解耦级，用于在输出缓冲器的切换瞬变期间使输出从电源线分离，以防止存在开关噪声 后者被传送到输出缓冲器的输出。