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    Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache
    1.
    发明授权
    Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache 失效
    将指令指针的虚拟地址转换为访问指令高速缓存的物理地址

    公开(公告)号：US5500948A

    公开(公告)日：1996-03-19

    申请号：US274214

    申请日：1994-07-13

    申请人： Glenn J. Hinton ,  Robert M. Riches, Jr.

    发明人： Glenn J. Hinton ,  Robert M. Riches, Jr.

    IPC分类号： G06F12/10 ,  G06F12/00

    CPC分类号： G06F12/1027

    摘要： A data processing system comprised of a memory, a translation lookaside buffer (TLB) providing access to the memory, and an instruction cache connected to the memory. A two entry translation write buffer (TWB) has a first entry that is a first logical register and an associated first physical address register and a second entry that is a second logical register and an associated second physical address register. A physical address bus is connected to the TWB and a logical address bus is connected to the TLB and to the TWB, the logical address bus presenting an instruction pointer to the TLB and to the TWB. The instruction pointer is comprised of logical address bits including upper order bits, lower order bits, and a single bit having a first value or a second value. The single bit provides for translation of even-number pages for which the single bit has the first value and for odd-number pages for which the single bit has the second value. The upper order bits of the logical address are compared with the stored address values in the first and second logical registers in the TWB resulting in a first hit signal with respect to the first logical register or a second hit signal with respect to the second logical register. The first logical register is selected if the single bit has the first value and the second logical register is selected if the single bit has the second value. The physical address bus is driven with the corresponding first or second physical address associated with a selected first or second logical register upon a condition that the upper order bits of the logical address equal a stored value in the first or second logical register in the TWB.

    摘要翻译： 包括存储器，提供对存储器的存取的翻译后备缓冲器（TLB）以及连接到存储器的指令高速缓存器的数据处理系统。 两个条目翻译写入缓冲器（TWB）具有第一条目，其是第一逻辑寄存器和相关联的第一物理地址寄存器，第二条目是第二逻辑寄存器和相关联的第二物理地址寄存器。 物理地址总线连接到TWB，并且逻辑地址总线连接到TLB和TWB，逻辑地址总线呈现指向TLB和TWB的指令指针。 指令指针由逻辑地址位组成，包括高位位，低位位和具有第一值或第二值的单位。 单个位提供用于单个位具有第一值的偶数页的翻译以及单个位具有第二个值的奇数页。 逻辑地址的高位与TWB中的第一和第二逻辑寄存器中存储的地址值进行比较，得到相对于第一逻辑寄存器的第一命中信号或相对于第二逻辑寄存器的第二命中信号 。 如果单个位具有第一个值，则选择第一个逻辑寄存器，如果单个位具有第二个值，则选择第二个逻辑寄存器。 在逻辑地址的高位等于TWB中的第一或第二逻辑寄存器中的存储值的条件下，物理地址总线被驱动与相应的与所选择的第一或第二逻辑寄存器相关联的第一或第二物理地址。

    Instruction fetch unit with early instruction fetch mechanism
    2.
    发明授权
    Instruction fetch unit with early instruction fetch mechanism 失效
    指令提取单元具有早期指令提取机制

    公开(公告)号：US5423014A

    公开(公告)日：1995-06-06

    申请号：US202710

    申请日：1994-02-24

    申请人： Glenn J. Hinton ,  Robert M. Riches, Jr.

    发明人： Glenn J. Hinton ,  Robert M. Riches, Jr.

    IPC分类号： G06F9/38 ,  G06F12/10 ,  G06F12/00

    CPC分类号： G06F9/3802 ,  G06F12/1027 ,  G06F2212/681

    摘要： An instruction fetch unit in which an early instruction fetch is initiated to access a main memory simultaneously with checking a cache for the desired instruction. On a slow path to main memory is a large main translation lookaside buffer (TLB) that holds address translations. On a fast path is a smaller translation write buffer (TWB), a mini-TLB, that holds recently used address translations. A guess fetch access in initiated by presenting an address to the main memory in parallel with presenting the address to the cache. The address is compared with the contents of the TWB for a hit and with the contents of the cache for a hit. The guess access is allowed to proceed upon the condition that there is a hit in the TWB (the TWB is able to translate the logical address into a physical address) and a miss in the I-cache (the data are not available in the I-cache and hence the guess access of main memory is necessary to get the data). The guess access is canceled upon the condition that there is either a miss in the TWB (the TWB is unable to translate the logical address into a physical address) or a hit in the I-cache (the data are available in the I-cache and hence the guess access of main memory is not necessary). In this case a fetch access is reissued on the "slow" path that goes through the large main TLB.

    摘要翻译： 指令提取单元，其中启动早期指令提取以同时检查主存储器以检查期望指令的高速缓存。 在主存储器的缓慢路径上是一个保存地址转换的大型主翻译后备缓冲区（TLB）。 在快速路径上是一个较小的翻译写缓冲区（TWB），一个mini-TLB，保存最近使用的地址转换。 通过向主存储器呈现地址并且向缓存呈现地址而发起的猜测获取访问。 将地址与TWB的内容进行比较，并将其与缓存的内容进行比较。 在TWB（TWB能够将逻辑地址转换为物理地址）和I-cache中的小命令（数据在I中不可用的情况下）允许进行猜测访问 -cache，因此获取数据需要主内存的猜测访问）。 在TWB（TWB无法将逻辑地址转换为物理地址）或I缓存中的命中（数据在I缓存中可用）的情况下，猜测访问被取消 因此不需要主存储器的猜测访问）。 在这种情况下，在通过大型主TLB的“慢”路径上重新发出提取访问。

    Machine check architecture execution environment for non-microcoded processor
    4.
    发明授权
    Machine check architecture execution environment for non-microcoded processor 有权
    非微处理器的机器检查体系结构执行环境

    公开(公告)号：US09141461B2

    公开(公告)日：2015-09-22

    申请号：US13924585

    申请日：2013-06-23

    申请人： Willam C. Rash ,  Scott D. Hanh ,  Glenn J. Hinton

    发明人： Willam C. Rash ,  Scott D. Hanh ,  Glenn J. Hinton

    IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14

    CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/1415 ,  G06F11/142 ,  G06F11/1443 ,  G06F2201/815

    摘要： A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error. The occurrence of the error causes a non-microcoded processing device to enter an error monitoring state. The method further processes the error using a dedicated memory portion for the error monitoring state while the non-microcoded processing device is in the error monitoring state. The error monitoring state is dedicated to error processing. The method further determines information associated with the error. The information associated with the error is in a predefined format.

    摘要翻译： 一种用于实现机器检查架构环境的方法的技术。 本公开的方法包括获得错误的发生。 错误的发生导致非微编码处理设备进入错误监视状态。 该方法使用专用存储器部分处理错误，用于错误监视状态，而非微编码处理设备处于错误监视状态。 错误监控状态专用于错误处理。 该方法进一步确定与错误相关联的信息。 与错误相关联的信息是预定义的格式。

    APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES
    5.
    发明申请
    APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 有权
    用于实现具有不同操作模式的多级记忆层次的装置和方法

    公开(公告)号：US20130268728A1

    公开(公告)日：2013-10-10

    申请号：US13994731

    申请日：2011-09-30

    申请人： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

    发明人： Raj K. Ramanujan ,  Rajat Agarwal ,  Glenn J. Hinton

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

    摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

    摘要翻译： 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。 更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。 这些更高性能的存储器件被称为“接近存储器”。 在一个实施例中，“近存储器”被配置为以多种不同的操作模式操作，包括（但不限于）其中近端存储器作为远存储器的存储器高速缓存操作的第一模式，以及第二模式 其中所述近存储器被分配有系统地址空间的第一地址范围，所述远存储器被分配了所述系统地址空间的第二地址范围，其中所述第一范围和第二范围表示整个系统地址空间。

    PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES
    7.
    发明申请
    PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES 审中-公开
    具有执行核心部分的处理器以不同的时钟速率运行

    公开(公告)号：US20120042151A1

    公开(公告)日：2012-02-16

    申请号：US12879872

    申请日：2010-09-10

    申请人： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    发明人： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    IPC分类号： G06F15/76 ,  G06F9/02

    CPC分类号： G06F9/3842 ,  G06F1/08 ,  G06F9/30145 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863 ,  G06F9/3869 ,  G06F15/7832

    摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

    摘要翻译： 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。 可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

    Processor having execution core sections operating at different clock rates
    10.
    发明授权
    Processor having execution core sections operating at different clock rates 有权
    具有执行核心部分以不同时钟速率工作的处理器

    公开(公告)号：US06256745B1

    公开(公告)日：2001-07-03

    申请号：US09527065

    申请日：2000-03-16

    申请人： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    发明人： David J. Sager ,  Thomas D. Fletcher ,  Glenn J. Hinton ,  Michael D. Upton

    IPC分类号： G06F106

    CPC分类号： G06F1/02 ,  G06F1/06 ,  G06F1/08 ,  G06F9/30145 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3869 ,  G06F15/7832

    摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

    摘要翻译： 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能比第一执行核心部分慢的I / O环，可选地，第一执行核心部分可以包括其时钟速率在第一和第二执行核心部分之间的时钟速率的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。