公开(公告)号：US20150024585A1

公开(公告)日：2015-01-22

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying LUO ,  Feng ZHOU ,  Yan Ping SHEN ,  Haiting WANG ,  Haoran SHI ,  Wei Hua TONG ,  Seung KIM ,  Yong Meng LEE

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。

公开(公告)号：US20160163702A1

公开(公告)日：2016-06-09

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Yue HU ,  Xin WANG ,  Yong Meng LEE ,  Wen-Pin PENG ,  Lun ZHAO ,  Wei-Hua TONG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions

Abstract translation: 公开了用于形成沟槽硅化物而不使硅源极/漏极区和所得到的器件气蚀的方法。 实施例包括在基板上形成第一和第二伪栅极，每个具有相对侧的间隔物; 在第一伪栅极的相对侧形成eSiGe源极/漏极区; 在所述第二虚拟栅极的相对侧形成凸起的源极/漏极区域; 在每个eSiGe和升高的源极/漏极区域上形成硅帽; 在第一和第二虚拟门之间和之间形成ILD; 分别用第一和第二HKMG代替第一和第二虚拟门; 在每个eSiGe和升高的源极/漏极区域上形成穿过ILD的接触沟槽进入硅帽; 并在eSiGe上形成硅化物并升高源极/漏极区域

公开(公告)号：US20160049488A1

公开(公告)日：2016-02-18

申请号：US14458941

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Haiting WANG ,  Min-hwa CHI ,  Yong Meng LEE

IPC: H01L29/423 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L29/42376 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled.

Abstract translation: 具有宽底部和/或宽顶部栅极的半导体结构包括半导体衬底，源极区域，与源极区域相关联的漏极区域以及与所述源极区域相关联的栅极 源极区和漏极区具有顶部和底部。 栅极的顶部和底部之一比顶部和底部中的另一个宽。 使用从虚拟栅极材料层蚀刻的虚拟宽底栅极创建宽底栅极，产生用于伪栅极的间隔物，去除虚拟栅极材料并填充由导电材料形成的开口。 对于宽顶栅，包括第一和第二间隔物，而不是去除所有的虚拟栅极材料，仅去除一部分，暴露第一间隔物。 第一间隔件的暴露部分可以被完全或部分地去除（例如，渐缩），以增加要填充的浇口顶部的面积。

公开(公告)号：US20150249136A1

公开(公告)日：2015-09-03

申请号：US14195330

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Feng ZHOU ,  Tien-Ying LUO ,  Haiting WANG ,  Padmaja NAGAIAH ,  Jean-Baptiste LALOE ,  Isabelle Pauline FERAIN ,  Yong Meng LEE

IPC: H01L29/40 ,  H01L21/311 ,  H01L29/51

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/3247 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.

Abstract translation: 提供了一种用于制造半导体器件的改进方法。 该方法包括：在基底上沉积电介质层; 在所述电介质层上沉积第一盖层; 在所述电介质层上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积虚拟盖层以形成部分栅极结构。 还提供了部分形成的半导体器件。 部分形成的半导体器件包括：衬底; 基底上的电介质层; 介电层上的第一盖层; 介电层上的蚀刻停止层; 以及形成部分栅极结构的蚀刻停止层上的虚设盖层。

公开(公告)号：US20140339612A1

公开(公告)日：2014-11-20

申请号：US13896022

申请日：2013-05-16

Applicant: GlobalFoundries Inc.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Meng LUO ,  Yong Meng LEE

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。