公开(公告)号：US20140339612A1

公开(公告)日：2014-11-20

申请号：US13896022

申请日：2013-05-16

Applicant: GlobalFoundries Inc.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Meng LUO ,  Yong Meng LEE

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。

公开(公告)号：US20190131452A1

公开(公告)日：2019-05-02

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Hong YU ,  Xinyuan DOU ,  Xusheng WU ,  Dongil CHOI ,  Edmund K. BANGHART ,  Md Khaled HASSAN

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US20190013245A1

公开(公告)日：2019-01-10

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Wei HONG ,  Wei ZHAO ,  Tae Jeong LEE ,  Zhenyu HU

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/7855 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/475 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/435 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2027/11805 ,  H01L2027/11831 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.