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    Fin selector with gated RRAM
    1.
    发明授权
    Fin selector with gated RRAM 有权

    公开(公告)号：US10424732B2

    公开(公告)日：2019-09-24

    申请号：US15729314

    申请日：2017-10-10

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

    Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same
    3.
    发明授权
    Integrated circuits having improved split-gate nonvolatile memory devices and methods for fabrication of same 有权
    具有改进的分离式非易失性存储器件的集成电路及其制造方法

    公开(公告)号：US08945997B2

    公开(公告)日：2015-02-03

    申请号：US13929393

    申请日：2013-06-27

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Zufa Zhang ,  Khee Yong Lim ,  Elgin Quek

    IPC: H01L21/82 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/42344 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/66833 ,  H01L29/792

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 一种用于制造具有分离栅非易失性存储器件的集成电路的示例性方法包括形成覆盖半导体衬底并具有第一侧壁和第二侧壁并形成内腔的电荷存储结构。 该方法在内腔中形成控制门。 此外，该方法形成覆盖半导体衬底并且邻近第一侧壁的第一选择栅极。 第一存储单元由控制栅极和第一选择栅极形成。 该方法还形成覆盖半导体衬底并邻近第二侧壁的第二选择栅极。 第二存储单元由控制栅极和第二选择栅极形成。

    SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE AND METHOD OF MANUFACTURING THEREOF
    4.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE AND METHOD OF MANUFACTURING THEREOF 有权
    具有降低接触电阻的半导体器件及其制造方法

    公开(公告)号：US20130270654A1

    公开(公告)日：2013-10-17

    申请号：US13915221

    申请日：2013-06-11

    Applicant: Globalfoundries Singapore PTE. LTD.

    Inventor： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

    IPC: H01L29/78

    CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66575

    Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

    Abstract translation: 制造半导体器件的方法（和半导体器件）提供具有降低的接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在接触硅化物形成之后，在源极/漏极（S / D）区域中注入杂质，并且进行尖峰退火处理，其降低硅化物和S / D层的下部结区之间的界面的肖特基势垒高度（SBH） D区。 这导致较低的接触电阻并且减小了硅化物半导体界面处的区域的厚度（和Rs）。

    Transistor devices having an anti-fuse configuration and methods of forming the same
    7.
    发明授权
    Transistor devices having an anti-fuse configuration and methods of forming the same 有权
    具有反熔丝结构的晶体管器件及其形成方法

    公开(公告)号：US09431497B2

    公开(公告)日：2016-08-30

    申请号：US13899150

    申请日：2013-05-21

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat Toh ,  Shyue Seng Tan ,  Elgin Quek

    IPC: H01L29/76 ,  H01L29/423 ,  H01L27/112 ,  G11C17/16 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L21/822 ,  H01L23/525

    CPC classification number: H01L29/42364 ,  G11C17/16 ,  H01L21/8221 ,  H01L23/5252 ,  H01L27/0688 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/11206 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/42388 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.

    Abstract translation: 提供具有反熔丝配置的晶体管器件和形成晶体管器件的方法。 示例性晶体管器件包括包括第一鳍片的半导体衬底。 第一绝缘体层覆盖半导体衬底并且具有小于第一鳍片的高度的厚度。 第一鳍延伸穿过第一绝缘体层并突出超过第一绝缘体层以提供掩埋鳍部分和暴露的鳍部分。 栅电极结构覆盖在暴露的鳍部上。 栅绝缘结构设置在第一鳍和栅电极结构之间。 栅极绝缘结构包括覆盖第一鳍片的第一表面的第一介电层。 栅极绝缘结构还包括覆盖第一鳍片的第二表面的第二介电层。 通过第一介电层在第一鳍片和栅极电极结构之间限定电势击穿路径。

    Corner transistor suppression
    8.
    发明授权
    Corner transistor suppression 有权
    角晶体管抑制

    公开(公告)号：US09368386B2

    公开(公告)日：2016-06-14

    申请号：US13927588

    申请日：2013-06-26

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Shyue Seng Tan ,  Ying Keung Leung ,  Elgin Quek

    IPC: H01L21/70 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234

    CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/088

    Abstract: The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.

    Abstract translation: 形成在浅沟槽隔离区域的角落处的寄生晶体管的阈值电压增加，并且通过使用高K介电材料使迁移率降低。 实施例包括STI区域，其包括在沟槽角附近延伸的高K电介质材料的衬垫。 实施例还包括具有形成在沟槽中的凹部的STI区域，其中凹部包含在沟槽角附近延伸的层或间隔物形式的高K电介质材料。

    NOVEL METHOD TO TUNE NARROW WIDTH EFFECT WITH RAISED S/D STRUCTURE
    9.
    发明申请
    NOVEL METHOD TO TUNE NARROW WIDTH EFFECT WITH RAISED S/D STRUCTURE 有权
    用增加的S / D结构调节NARROW宽度效应的新方法

    公开(公告)号：US20140332902A1

    公开(公告)日：2014-11-13

    申请号：US14338012

    申请日：2014-07-22

    Applicant: Globalfoundries Singapore PTE. LTD.

    Inventor： Chunshan Yin ,  Guangyu Huang ,  Elgin Quek ,  Jae Gon Lee ,  Kian Ming Tan

    IPC: H01L27/088 ,  H01L29/10 ,  H01L29/08

    CPC classification number: H01L27/088 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/7848

    Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

    Abstract translation: 制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。 以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。 在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。 结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

    LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode
    10.
    发明授权
    LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode 有权

    公开(公告)号：US10032902B2

    公开(公告)日：2018-07-24

    申请号：US14713819

    申请日：2015-05-15

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

    Abstract: An LDMOS is formed with a second gate stack over n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.

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