公开(公告)号：US20120037962A1

公开(公告)日：2012-02-16

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US08232618B2

公开(公告)日：2012-07-31

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L29/00

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US08390079B2

公开(公告)日：2013-03-05

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L27/088

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US20120199886A1

公开(公告)日：2012-08-09

申请号：US13020107

申请日：2011-02-03

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/7833

摘要： A semiconductor chip, including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a source and a drain in the substrate adjacent to the gate; a tapered contact contacting a portion of one of the source or the drain; and a sealed air gap between the sidewall and the contact.

摘要翻译： 一种半导体芯片，包括基板; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 邻近栅极的衬底中的源极和漏极; 与所述源极或所述漏极中的一个的一部分接触的锥形接触; 以及侧壁和接触件之间的密封气隙。

公开(公告)号：US20120104512A1

公开(公告)日：2012-05-03

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US20120068346A1

公开(公告)日：2012-03-22

申请号：US12885665

申请日：2010-09-20

申请人： SHOM PONOTH ,  David V. Horak ,  Elbert E. Huang ,  Sivananda K. Kanakasabapathy ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： SHOM PONOTH ,  David V. Horak ,  Elbert E. Huang ,  Sivananda K. Kanakasabapathy ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/53266 ,  H01L21/32139 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

摘要翻译： 为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。 在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。 通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

公开(公告)号：US08030202B1

公开(公告)日：2011-10-04

申请号：US12964831

申请日：2010-12-10

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor contacts the substrate. Next, the method selectively removes the sacrificial material, to create at least one “second” opening along the metallic conductor within the first opening. The method selectively removes portions of the first insulator layer through the second opening to leave at least one air gap between the metallic conductor and the first insulator layer in the lower region of the second opening.

摘要翻译： 示例性方法用牺牲材料排列第一开口的侧壁，然后以金属导体接触基板的方式用金属导体填充第一开口。 接下来，该方法选择性地去除牺牲材料，以在第一开口内沿着金属导体产生至少一个“第二”开口。 所述方法通过所述第二开口选择性地去除所述第一绝缘体层的部分，以在所述第二开口的下部区域中留下所述金属导体和所述第一绝缘体层之间的至少一个气隙。

公开(公告)号：US20140061930A1

公开(公告)日：2014-03-06

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

公开(公告)号：US08609534B2

公开(公告)日：2013-12-17

申请号：US12890941

申请日：2010-09-27

申请人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/4763

CPC分类号： H01L23/5256 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.

摘要翻译： 使用位于金属层顶部的双镶嵌结构来提供高编程效率电熔丝。 双镶嵌结构包括图案化电介质材料，其具有位于下面的通孔开口上方并连接到下面的通孔开口的线路开口。 通孔开口位于顶部并连接到金属层。 双镶嵌结构还包括线路开口和通孔开口内的导电特征。 电介质间隔物也存在于线路开口和通孔开口内。 介电间隔物存在于图案化电介质材料的垂直侧壁上，并将导电特征与图案化电介质材料分开。 在线路开口和通孔开口内的电介质间隔物的存在减少了形成导电特征的区域。 因此，提供了节省空间的高编程效率电熔丝。

公开(公告)号：US20130328208A1

公开(公告)日：2013-12-12

申请号：US13490542

申请日：2012-06-07

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。