公开(公告)号：US20120037962A1

公开(公告)日：2012-02-16

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US08390079B2

公开(公告)日：2013-03-05

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L27/088

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US20120199886A1

公开(公告)日：2012-08-09

申请号：US13020107

申请日：2011-02-03

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/7833

摘要： A semiconductor chip, including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a source and a drain in the substrate adjacent to the gate; a tapered contact contacting a portion of one of the source or the drain; and a sealed air gap between the sidewall and the contact.

摘要翻译： 一种半导体芯片，包括基板; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 邻近栅极的衬底中的源极和漏极; 与所述源极或所述漏极中的一个的一部分接触的锥形接触; 以及侧壁和接触件之间的密封气隙。

公开(公告)号：US08232618B2

公开(公告)日：2012-07-31

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L29/00

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US20120104512A1

公开(公告)日：2012-05-03

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, JR. ,  Shom Ponoth

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US08030202B1

公开(公告)日：2011-10-04

申请号：US12964831

申请日：2010-12-10

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An exemplary method lines the sidewalls of a first opening with a sacrificial material and then fills the first opening with a metallic conductor in a manner such that the metallic conductor contacts the substrate. Next, the method selectively removes the sacrificial material, to create at least one “second” opening along the metallic conductor within the first opening. The method selectively removes portions of the first insulator layer through the second opening to leave at least one air gap between the metallic conductor and the first insulator layer in the lower region of the second opening.

摘要翻译： 示例性方法用牺牲材料排列第一开口的侧壁，然后以金属导体接触基板的方式用金属导体填充第一开口。 接下来，该方法选择性地去除牺牲材料，以在第一开口内沿着金属导体产生至少一个“第二”开口。 所述方法通过所述第二开口选择性地去除所述第一绝缘体层的部分，以在所述第二开口的下部区域中留下所述金属导体和所述第一绝缘体层之间的至少一个气隙。

公开(公告)号：US20120068346A1

公开(公告)日：2012-03-22

申请号：US12885665

申请日：2010-09-20

申请人： SHOM PONOTH ,  David V. Horak ,  Elbert E. Huang ,  Sivananda K. Kanakasabapathy ,  Charles W. Koburger, III ,  Chih-Chao Yang

发明人： SHOM PONOTH ,  David V. Horak ,  Elbert E. Huang ,  Sivananda K. Kanakasabapathy ,  Charles W. Koburger, III ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/53266 ,  H01L21/32139 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

摘要翻译： 为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。 在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。 通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

公开(公告)号：US20130009282A1

公开(公告)日：2013-01-10

申请号：US13614524

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/06

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

公开(公告)号：US08288268B2

公开(公告)日：2012-10-16

申请号：US12770254

申请日：2010-04-29

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/40 ,  H01L21/4763

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。

公开(公告)号：US09105693B2

公开(公告)日：2015-08-11

申请号：US13614563

申请日：2012-09-13

申请人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

发明人： Daniel C. Edelstein ,  David V. Horak ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Takeshi Nogami ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L29/40 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H05K1/0216 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H05K1/0298 ,  H05K1/03 ,  H05K2201/0707 ,  H05K2201/09063

摘要： A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.

摘要翻译： 微电子结构和微电子结构的制造方法提供插入在多个导体层之间的多个空隙。 多个空隙也位于衬垫层和层间电介质层之间。 空隙提供了微电子结构的增强的电性能。