公开(公告)号：US08390079B2

公开(公告)日：2013-03-05

申请号：US12914132

申请日：2010-10-28

申请人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L27/088

CPC分类号： H01L29/4991 ,  H01L21/823468 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545

摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.

摘要翻译： 一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

公开(公告)号：US08232618B2

公开(公告)日：2012-07-31

申请号：US12854352

申请日：2010-08-11

申请人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

发明人： Gregory Breyta ,  David V. Horak ,  Elbert E. Huang ,  Charles W. Koburger, III ,  Douglas C. La Tulipe, Jr. ,  Shom Ponoth

IPC分类号： H01L29/00

CPC分类号： H01L21/7682 ,  H01L21/31144 ,  H01L23/4821 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5329 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.

摘要翻译： 公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。 具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。 定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。 还公开了使用自组装方法形成这种半导体结构的方法的实施例。

公开(公告)号：US09318375B2

公开(公告)日：2016-04-19

申请号：US12540490

申请日：2009-08-13

申请人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

发明人： Douglas C. La Tulipe, Jr. ,  Mark Todhunter Robson

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L27/06

CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L27/0688 ,  H01L2224/80896 ,  H01L2224/9202

摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三介电层，用对第一和第二电介质层选择的工艺蚀刻第二和第三介电层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。

公开(公告)号：US07241696B2

公开(公告)日：2007-07-10

申请号：US10318606

申请日：2002-12-11

申请人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

发明人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：US07001835B2

公开(公告)日：2006-02-21

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik A. Kumar ,  Stephen M. Rossnagel ,  Andrew H. Simon ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/4763

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ-cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US08940554B2

公开(公告)日：2015-01-27

申请号：US13359970

申请日：2012-01-27

申请人： Nathaniel C. Berliner ,  Kangguo Cheng ,  Toshiharu Furukawa ,  Douglas C. La Tulipe, Jr. ,  William R. Tonti

发明人： Nathaniel C. Berliner ,  Kangguo Cheng ,  Toshiharu Furukawa ,  Douglas C. La Tulipe, Jr. ,  William R. Tonti

IPC分类号： H01L21/306 ,  H01L21/66 ,  H01L21/302 ,  H01L21/762

CPC分类号： H01L22/20 ,  H01L21/302 ,  H01L21/30604 ,  H01L21/76254 ,  H01L22/12

摘要： A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

摘要翻译： 一种制造具有均匀厚度的非常薄的绝缘上绝缘体（ETSOI）层的方法包括：测量多个位置上绝缘体上半导体（SOI）层的厚度; 确定所述多个位置中的每一个处的去除厚度; 以及在所述多个位置处注入离子。 基于多个位置中的每个位置处的去除厚度动态地进行植入。 该方法还包括氧化SOI层以形成氧化物层，并除去氧化物层。

公开(公告)号：US08765578B2

公开(公告)日：2014-07-01

申请号：US13489861

申请日：2012-06-06

申请人： Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

发明人： Douglas C. La Tulipe, Jr. ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

IPC分类号： H01L21/30

CPC分类号： H01L25/50 ,  H01L23/562 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.

摘要翻译： 边缘保护键合半导体晶片的方法。 第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。 作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。 第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。 作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。 第一，第二和第三半导体晶片形成晶片叠层。 晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。

公开(公告)号：US08637953B2

公开(公告)日：2014-01-28

申请号：US12172452

申请日：2008-07-14

申请人： Douglas C. La Tulipe, Jr. ,  Sampath Purushothaman ,  James Vichiconti

发明人： Douglas C. La Tulipe, Jr. ,  Sampath Purushothaman ,  James Vichiconti

IPC分类号： H01L21/70

CPC分类号： H01L21/3065 ,  C23C16/402 ,  C23C16/513 ,  C23C16/56 ,  H01L21/02002 ,  H01L21/187 ,  H01L21/3221 ,  H01L21/67063 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/77 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/06 ,  H01L2221/68377 ,  H01L2224/83121 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

摘要翻译： 描述了由其制造的三维集成器件和三维集成器件的制造。 施主晶片的器件侧涂覆有聚合物膜，并且将衬底侧暴露于氧化等离子体产生连续的SiO 2膜。 衬底侧的部分被选择性地涂覆聚合物膜，并且未涂覆区域的蚀刻除去至少大部分结晶衬底。 等离子体蚀刻工具将结晶衬底蚀刻到预定厚度内。 通过暴露于TMAH来蚀刻衬底侧的硅部分。 在蚀刻之后，施主半导体晶片由未被蚀刻的基板的部分支撑。 支撑结构允许施主半导体晶片在蚀刻区域内弯曲，以使得能够与受主晶片的器件表面保持一致并可靠地结合以形成三维集成器件。

公开(公告)号：US08637358B1

公开(公告)日：2014-01-28

申请号：US13542003

申请日：2012-07-05

申请人： Charles William Koburger, III ,  Douglas C. La Tulipe, Jr.

发明人： Charles William Koburger, III ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795

摘要： Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.

摘要翻译： 本发明的实施例提供了一种形成具有具有自对准扩散接触的替代栅电极的鳍式晶体管的方法。 该方法包括在氧化物层的顶部上形成一个或多个硅散热片，氧化物层位于硅供体晶片的顶部; 形成与所述一个或多个硅散热片交叉的一个或多个虚拟栅电极; 在所述一个或多个虚拟栅电极的侧壁旁边形成侧壁间隔物; 去除所述氧化物层的一个或多个区域，从而在其中形成开口，所述开口与所述侧壁间隔物的所述一个或多个翅片和边缘的边缘自对准; 在所述开口中形成外延硅层; 去除施主晶片; 并且至少硅化外延硅层的底部。 还提供了由此形成的半导体结构。

公开(公告)号：US08592270B2

公开(公告)日：2013-11-26

申请号：US13115314

申请日：2011-05-25

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, Jr.

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, Jr.

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807

摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.

摘要翻译： 形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。