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1.发明授权System for bus monitoring using a reconfigurable bus monitor which is adapted to report back to CPU in response to detecting certain selected events 有权用于使用可重配置总线监视器进行总线监视的系统，其适于响应于检测到某些所选择的事件而向CPU报告公开(公告)号：US06931524B2
公开(公告)日：2005-08-16
申请号：US09942129
申请日：2001-08-29
申请人： Gregory E. Ehmann , Swati Saxena
发明人： Gregory E. Ehmann , Swati Saxena
CPC分类号： G06F11/349 , G06F2201/86
摘要： An adaptive data communication approach permits communication bus monitoring by using a reconfigurable bus monitor built into the CPU bus structure and adapted to report back to the CPU in response to detecting certain CPU-programmed events. In one particular example embodiment, a circuit arrangement having a CPU circuit communicates with another device over a communication channel while a reconfigurable circuit monitors the communication channel. The CPU circuit configures the reconfigurable circuit for monitoring any of various types of event expected to occur on the communication channel. The reconfigurable circuit collects signals passed on the communication channel and reports back to the CPU circuit when data indicative of the first event type occurs on the communication channel. In response to the data indicative of the monitored event, the CPU circuit reconfigures the reconfigurable circuit to monitor for another event type occurring on the communication channel and thereby permits for an adaptive evaluation of the communication channel. Another aspect of the invention is directed to the CPU redirecting data communication in response to this adaptive evaluation.
摘要翻译： 自适应数据通信方法允许通过使用内置在CPU总线结构中的可重配置总线监视器进行通信总线监视，并且适于响应于检测到某些CPU编程的事件而向CPU报告。 在一个特定示例实施例中，具有CPU电路的电路装置通过通信信道与另一设备通信，而可重构电路监视通信信道。 CPU电路配置可重构电路，用于监视预期在通信信道上发生的各种类型的事件中的任何一种。 当在通信信道上发生指示第一事件类型的数据时，可重新配置电路收集在通信信道上传递的信号并且向CPU电路报告。 响应于指示监视事件的数据，CPU电路重新配置可重构电路以监视在通信信道上发生的另一事件类型，从而允许通信信道的自适应评估。 本发明的另一方面涉及CPU响应于该自适应评估重定向数据通信。
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公开(公告)号：US06920576B2
公开(公告)日：2005-07-19
申请号：US09871117
申请日：2001-05-31
申请人： Gregory E. Ehmann
发明人： Gregory E. Ehmann
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/04 , H04L25/4908
摘要： A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.
摘要翻译： 高速并行数据通信方法通过自动对准传输数字数据来克服偏斜问题。 在一个示例实施例中，并行总线具有适于从数据文件传送数字数据的并行总线以及同步时钟信号。 为了校准同步，发送模块通过接收模块传输根据时钟信号的边沿进行采样和验证的同步码，然后用于相对于同步码对时钟信号的边沿进行时间调整。 执行同步代码以在传送了每个同步码的情况下切换总线。
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公开(公告)号：US20100174521A1
公开(公告)日：2010-07-08
申请号：US11720824
申请日：2005-12-02
IPC分类号： G06G7/62
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Various aspects of the present invention are directed to design modeling and/or processing of streaming data. According to an example embodiment, a system to model a hardware specification includes a platform (106) arranged to receive an input data stream and transmit an output data stream. The system also includes a source (102) for a streaming application adapted to provide the input data stream at a source data rate, a destination (104) for the streaming application adapted to consume the output data stream at a destination data rate, and a data channel (110) coupling the platform and a computer (108). The computer uses the hardware specification to generate intermediate data streams, which, in turn, are used to streamline the modeling for the platform.
摘要翻译： 本发明的各个方面涉及流数据的设计建模和/或处理。 根据示例实施例，用于建模硬件规范的系统包括布置成接收输入数据流并发送输出数据流的平台（106）。 该系统还包括用于适于以源数据速率提供输入数据流的流应用的源（102），适用于以目的数据速率消耗输出数据流的流应用的目的地（104），以及 耦合平台的数据通道（110）和计算机（108）。 计算机使用硬件规范来生成中间数据流，这又用于简化平台的建模。
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公开(公告)号：US07085950B2
公开(公告)日：2006-08-01
申请号：US09966297
申请日：2001-09-28
CPC分类号： H04L7/0008 , H04L25/14
摘要： A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
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公开(公告)号：US06507887B1
公开(公告)日：2003-01-14
申请号：US09551087
申请日：2000-04-18
IPC分类号： G06F1200
CPC分类号： G06F1/3275 , G06F1/3203 , G11C7/06 , G11C17/12 , G11C2207/2227 , Y02D10/126 , Y02D10/13 , Y02D10/14
摘要： A method of designing a mask-programmable random-access read-only memory device begins with a step of assigning weightings to addresses according to their expected frequency of access. These weighting are used in a second step of determining for each sense amplifier, what is the low-power sense (inverted or uninverted) of the stored bits using that sense amplifier as an output. The third step involves storing the data in the low-power sense. The fourth step involves inverting the outputs for the data that is stored inverted. This can involve using sense inverting sense amplifiers for inverted data and sense preserving amplifiers for uninverted data. The method can result in memories in which some outputs are sense inverting while others are sense preserving. The result is a memory device with reduced power consumption relative to a comparable design not taking advantage of the relationship between data values and power consumption.
摘要翻译： 设计掩模可编程随机访问只读存储器设备的方法开始于根据其预期访问频率向地址分配加权的步骤。 这些加权用于确定每个读出放大器的第二步骤中，使用该读出放大器作为输出的存储位的低功率检测（反相或未反相）是多少。 第三步涉及将数据存储在低功耗意义上。 第四步涉及反转存储的数据的输出。 这可以涉及使用用于反相数据的感测反相读出放大器和用于未反转数据的感测保持放大器。 该方法可以导致其中一些输出是有意义的反相的存储器，而另一些是有意义的保留。 结果是相对于不利用数据值和功耗之间的关系的类似设计，具有降低的功耗的存储器件。
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6.发明授权Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs 失效集成电路设计中有效实现复杂功能块的方法和装置
公开(公告)号：US5963454A
公开(公告)日：1999-10-05
申请号：US719610
申请日：1996-09-25
CPC分类号： G06F17/5045
摘要： A method in accordance with the present invention for developing an integrated circuit design using a compilation tool includes: (A) developing at least one HDL template by: (a) creating the HDL template; (b) creating a parameter file and a parameter check file for the HDL template; and (c) encrypting the HDL template; (B) developing design specifications for use in creating HDL for synthesis and for use in compiling one or more macro blocks; (C) creating the HDL for synthesis; and (D) creating netlists for at least one macro block instantiated in the HDL template using the design specifications. A development tool of the present invention implements the method on a computer system to form a portion of an integrated circuit fabrication system.
摘要翻译： 根据本发明的用于使用编译工具开发集成电路设计的方法包括：（A）通过以下步骤开发至少一个HDL模板：（a）创建HDL模板; （b）为HDL模板创建参数文件和参数检查文件; 和（c）加密HDL模板; （B）制定用于创建HDL以用于编译一个或多个宏块的设计规范; （C）创建用于合成的HDL; 和（D）使用设计规范为HDL模板中实例化的至少一个宏块创建网表。 本发明的开发工具在计算机系统上实现了形成集成电路制造系统的一部分的方法。
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公开(公告)号：US5666068A
公开(公告)日：1997-09-09
申请号：US552666
申请日：1995-11-03
申请人： Gregory E. Ehmann
发明人： Gregory E. Ehmann
IPC分类号： H03K3/3565 , H03K19/0185
CPC分类号： H03K19/018528 , H03K3/3565
摘要： A GTL input receiver for receiving differential GTL signals and for generating a CMOS output at a single-ended output terminal includes a comparator circuit, a current-to-voltage converter circuit, and an inverter. The comparator is formed of a first primary current steering device and a second primary current steering device. Auxiliary current steering devices are coupled to the first and second primary current steering devices for adding hysteresis by dynamically changing the ratio of the currents flowing through the first and second primary current source devices. The input receiver also includes a control circuit for selectively enabling and disabling the secondary current steering devices. As a result, the GTL input receiver has a hysteresis in the range of 50 mV to 200 mV and higher.
摘要翻译： 用于接收差分GTL信号并在单端输出端产生CMOS输出的GTL输入接收器包括比较器电路，电流 - 电压转换器电路和反相器。 比较器由第一初级电流转向装置和第二初级电流转向装置形成。 辅助电流转向装置耦合到第一和第二初级电流转向装置，用于通过动态地改变流过第一和第二初级电流源装置的电流的比例来增加滞后。 输入接收器还包括用于选择性地启用和禁用辅助电流转向装置的控制电路。 结果，GTL输入接收器的滞后在50 mV至200 mV及更高的范围内。
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公开(公告)号：US07020807B2
公开(公告)日：2006-03-28
申请号：US09955704
申请日：2001-09-19
申请人： Gregory E. Ehmann , Neil Gregie , Arjan Bink
发明人： Gregory E. Ehmann , Neil Gregie , Arjan Bink
IPC分类号： G06F11/00
CPC分类号： G06F13/423
摘要： A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput. In another aspect of the present invention, a computer system includes a test-traffic generator.
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公开(公告)号：US06839862B2
公开(公告)日：2005-01-04
申请号：US09871159
申请日：2001-05-31
CPC分类号： H04L7/0008 , H04L25/14
摘要： In one example embodiment, a high-speed parallel-data communication approach transfers digital data in parallel from a first module to a second module over a communication channel including a plurality of parallel data-carrying lines and a clock path. The parallel bus lines are arranged in a plurality of groups, each of the groups including a plurality of data-carrying lines and a clock path adapted to carry a clock signal for synchronizing digital data carried from the first module to the second module. The sets of data are concurrently transferred using the groups of lines of the parallel bus, and at the second module and for each group, the transferred digital data is synchronously collected via the clock signal for the group. At the second module, the data collected for each group is aligned. By grouping the bus lines in groups with each group having its own clock domain, skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
摘要翻译： 在一个示例实施例中，高速并行数据通信方法通过包括多个并行数据携带线路和时钟路径的通信信道将数字数据从第一模块并行传送到第二模块。 并行总线布置成多个组，每个组包括多个数据传送线和适于承载时钟信号的时钟路径，用于将从第一模块承载的数字数据同步到第二模块。 使用并行总线的线路并行传送数据组，并且在第二模块处，并且对于每个组，经由该组的时钟信号同步地收集传送的数字数据。 在第二个模块中，对每个组收集的数据进行对齐。 通过将每个组具有自己的时钟域的组中的总线分组，通过在每个时钟域组内，然后在组之间首先处理数据和偏移来容忍和克服时钟域组之间的偏斜。
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10.发明授权FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle 失效FIFO缓冲器，可以读取和/或写入每个总线周期的多个和/或可选数量的数据字公开(公告)号：US06701390B2
公开(公告)日：2004-03-02
申请号：US09875376
申请日：2001-06-06
申请人： Gregory E. Ehmann
发明人： Gregory E. Ehmann
IPC分类号： G06F1300
CPC分类号： G06F5/10
摘要： A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.
摘要翻译： 先进先出（FIFO）循环缓冲器通过具有多个端口来寻址存储器阵列来单向执行多个数据元件传输，从而实现集成电路器件之间的高速流数据传输。 此外，在一个总线周期期间执行多次传送，并且可以选择传送次数。 FIFO控制电路限制响应于几乎为空或几乎满的存储器阵列的状态传送的数据元件的数量。
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