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    Tunable multi-band receiver
    1.
    发明授权
    Tunable multi-band receiver 有权
    可调谐多频段接收机

    公开(公告)号：US09002309B2

    公开(公告)日：2015-04-07

    申请号：US13118283

    申请日：2011-05-27

    申请人： Gurkanwal Singh Sahota ,  Steven C. Ciccarelli ,  Sang-June Park ,  Charles J. Persico

    发明人： Gurkanwal Singh Sahota ,  Steven C. Ciccarelli ,  Sang-June Park ,  Charles J. Persico

    IPC分类号： H04B1/18 ,  H04B1/00 ,  H04B1/10 ,  H03H7/01

    CPC分类号： H04B1/525 ,  H03H2007/013 ,  H04B1/006 ,  H04B1/1036

    摘要： A tunable multi-band receiver supporting operation on a plurality of frequency bands is disclosed. In an exemplary design, the tunable multi-band receiver includes an antenna tuning network, a tunable notch filter, and at least one low noise amplifier (LNA). The antenna tuning network tunes an antenna (e.g., a diversity antenna) to a receive band in a plurality of receive bands. The tunable notch filter is tunable to a transmit band in a plurality of transmit bands and attenuates signal components in the transmit band. One LNA among the at least one LNA amplifies an output signal from the tunable notch filter. The tunable multi-band receiver may further include one or more additional tunable notch filters to further attenuate the signal components in the transmit band.

    摘要翻译： 公开了一种在多个频带上支持操作的可调谐多频带接收机。 在示例性设计中，可调谐多频带接收机包括天线调谐网络，可调谐陷波滤波器和至少一个低噪声放大器（LNA）。 天线调谐网络将天线（例如，分集天线）调谐到多个接收频带中的接收频带。 可调陷波滤波器可调谐到多个发射频带中的发射频带，并衰减发射频带中的信号分量。 至少一个LNA中的一个LNA放大来自可调陷波滤波器的输出信号。 可调谐多频带接收机还可以包括一个或多个附加可调陷波滤波器，以进一步衰减发射频带中的信号分量。

    TUNABLE MULTI-BAND RECEIVER
    2.
    发明申请
    TUNABLE MULTI-BAND RECEIVER 有权
    TUNABLE多带接收器

    公开(公告)号：US20120302188A1

    公开(公告)日：2012-11-29

    申请号：US13118283

    申请日：2011-05-27

    申请人： Gurkanwal Singh Sahota ,  Steven C. Ciccarelli ,  Sang-June Park ,  Charles J. Persico

    发明人： Gurkanwal Singh Sahota ,  Steven C. Ciccarelli ,  Sang-June Park ,  Charles J. Persico

    IPC分类号： H04B1/18

    CPC分类号： H04B1/525 ,  H03H2007/013 ,  H04B1/006 ,  H04B1/1036

    摘要： A tunable multi-band receiver supporting operation on a plurality of frequency bands is disclosed. In an exemplary design, the tunable multi-band receiver includes an antenna tuning network, a tunable notch filter, and at least one low noise amplifier (LNA). The antenna tuning network tunes an antenna (e.g., a diversity antenna) to a receive band in a plurality of receive bands. The tunable notch filter is tunable to a transmit band in a plurality of transmit bands and attenuates signal components in the transmit band. One LNA among the at least one LNA amplifies an output signal from the tunable notch filter. The tunable multi-band receiver may further include one or more additional tunable notch filters to further attenuate the signal components in the transmit band.

    摘要翻译： 公开了一种在多个频带上支持操作的可调谐多频带接收机。 在示例性设计中，可调谐多频带接收机包括天线调谐网络，可调谐陷波滤波器和至少一个低噪声放大器（LNA）。 天线调谐网络将天线（例如，分集天线）调谐到多个接收频带中的接收频带。 可调陷波滤波器可调谐到多个发射频带中的发射频带，并衰减发射频带中的信号分量。 至少一个LNA中的一个LNA放大来自可调陷波滤波器的输出信号。 可调谐多频带接收机还可以包括一个或多个附加可调陷波滤波器，以进一步衰减发射频带中的信号分量。

    Local oscillator buffer and mixer having adjustable size
    7.
    发明授权
    Local oscillator buffer and mixer having adjustable size 有权
    具有可调大小的本地振荡器缓冲器和混频器

    公开(公告)号：US08019310B2

    公开(公告)日：2011-09-13

    申请号：US11955201

    申请日：2007-12-12

    申请人： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

    发明人： Gurkanwal Singh Sahota ,  Frederic Bossu ,  Ojas M. Choksi

    IPC分类号： H04B1/26 ,  H04B7/00 ,  H04B15/00

    CPC分类号： H03D7/1441 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0084 ,  H03D2200/009

    摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.

    摘要翻译： 公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。 在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。 在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。 公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

    High-linearity complementary amplifier
    8.
    发明授权
    High-linearity complementary amplifier 有权
    高线性互补放大器

    公开(公告)号：US07936217B2

    公开(公告)日：2011-05-03

    申请号：US11947570

    申请日：2007-11-29

    申请人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Solti Peng

    发明人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Solti Peng

    IPC分类号： H03F3/18

    CPC分类号： H03F1/3205 ,  H03F1/0261 ,  H03F1/086 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/19 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2200/18 ,  H03F2200/294 ,  H03F2200/354 ,  H03F2200/451

    摘要： A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.

    摘要翻译： 互补放大器包括以堆叠配置耦合到PMOS晶体管的NMOS晶体管。 NMOS晶体管和PMOS晶体管接收和放大输入信号。 NMOS和PMOS晶体管作为线性互补放大器工作并提供输出信号。 NMOS和PMOS晶体管可以具有单独的偏置电压，其可以被选择为与这些晶体管的跨导的低到高和高到低的跃迁重叠。 可以选择NMOS和PMOS晶体管的宽度和长度尺寸以匹配输入电容的变化和中等反转区中NMOS晶体管的跨导变化，随着输入电容的变化和PMOS晶体管的跨导变化 中等反转区。 互补放大器可以具有近似恒定的总输入电容和在一定范围的电压上的近似恒定的总跨导。

    DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER
    9.
    发明申请
    DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
    数字锁相环与定位的时间到数字转换器

    公开(公告)号：US20090175399A1

    公开(公告)日：2009-07-09

    申请号：US11969359

    申请日：2008-01-04

    申请人： Bo Sun ,  Gurkanwal Singh Sahota ,  Zixiang Yang

    发明人： Bo Sun ,  Gurkanwal Singh Sahota ,  Zixiang Yang

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0802 ,  H03L7/087

    摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

    摘要翻译： 数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。 定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。 控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。 在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号 以获得TDC的第一个时钟信号。

    HIGH-LINEARITY COMPLEMENTARY AMPLIFIER
    10.
    发明申请
    HIGH-LINEARITY COMPLEMENTARY AMPLIFIER 有权
    高线性互补放大器

    公开(公告)号：US20090140812A1

    公开(公告)日：2009-06-04

    申请号：US11947570

    申请日：2007-11-29

    申请人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Solti Peng

    发明人： Junxiong Deng ,  Gurkanwal Singh Sahota ,  Solti Peng

    IPC分类号： H03F3/16

    CPC分类号： H03F1/3205 ,  H03F1/0261 ,  H03F1/086 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/19 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2200/18 ,  H03F2200/294 ,  H03F2200/354 ,  H03F2200/451

    摘要： A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.

    摘要翻译： 互补放大器包括以堆叠配置耦合到PMOS晶体管的NMOS晶体管。 NMOS晶体管和PMOS晶体管接收和放大输入信号。 NMOS和PMOS晶体管作为线性互补放大器工作并提供输出信号。 NMOS和PMOS晶体管可以具有单独的偏置电压，其可以被选择为与这些晶体管的跨导的低到高和高到低的跃迁重叠。 可以选择NMOS和PMOS晶体管的宽度和长度尺寸以匹配输入电容的变化和中等反转区中NMOS晶体管的跨导变化，随着输入电容的变化和PMOS晶体管的跨导变化 中等反转区。 互补放大器可以具有近似恒定的总输入电容和在一定范围的电压上的近似恒定的总跨导。