公开(公告)号：US5368687A

公开(公告)日：1994-11-29

申请号：US31572

申请日：1993-03-15

申请人： Gurtej S. Sandhu ,  Donald L. Westmoreland ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Donald L. Westmoreland ,  Pierre Fazan

IPC分类号： C04B35/01 ,  H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116 ,  C04B35/01 ,  H01L21/31122

摘要： In one aspect of the invention, a semiconductor processing method includes the following steps: a) providing a layer of an insulating inorganic metal oxide material atop a semiconductor wafer; b) subjecting the wafer with exposed insulating inorganic metal oxide material to dry etching conditions using a halogen or pseudohalogen based chemistry to react the insulating inorganic metal oxide material into solid halogenated or pseudohalogenated material; and c) reacting the solid halogenated or pseudohalogenated material with a gaseous organic ligand precursor to form a gaseous metal organic coordination complex incorporating the organic ligand precursor and to form a gaseous halogenated or pseudohalogenated species which are expelled from the wafer. In another aspect, a semiconductor processing method of removing or otherwise cleaning metal from a semiconductor wafer includes the following steps: a) subjecting a semiconductor wafer having exposed metal to a dry halogen or pseudohalogen gas to react the metal into solid halogenated or pseudohalogenated material; and b) reacting the solid halogenated or pseudohalogenated material with a gaseous organic ligand precursor to form a gaseous metal organic coordination complex incorporating the organic ligand precursor and metal, and to form a gaseous halogenated or pseudohalogenated species, the complex and species being expelled from the wafer. Alternately, the metal is directly incorporated with the gaseous organic ligand precursor without previous halogenation.

摘要翻译： 在本发明的一个方面，一种半导体处理方法包括以下步骤：a）在半导体晶片的顶部设置绝缘无机金属氧化物层; b）使用暴露的绝缘无机金属氧化物材料的晶片对干蚀刻条件进行干燥，使用卤素或基于假卤素的化学反应将绝缘无机金属氧化物材料反应成固体卤化或假卤化材料; 和c）使固体卤化或假卤素材料与气态有机配体前体反应，形成掺入有机配体前体的气态金属有机配位络合物，并形成从晶片排出的气态卤化或假卤化物质。 另一方面，从半导体晶片去除或以其他方式清除金属的半导体处理方法包括以下步骤：a）使具有暴露金属的半导体晶片经干卤素或拟卤素气体使金属反应成固体卤化或假卤素材料; 和b）使固体卤化或假卤素材料与气态有机配体前体反应，形成结合有机配体前体和金属的气态金属有机配位络合物，并形成气态卤化或假卤化物质，复合物和物质从 晶圆。 或者，金属直接与气态有机配体前体结合，而无需先前的卤化。

公开(公告)号：US06936549B2

公开(公告)日：2005-08-30

申请号：US10737500

申请日：2003-12-16

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L27/10852

摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

摘要翻译： 在半导体工艺中在半导体衬底上沉积多组分层。 多组分层可以是由气态钛有机金属前体，反应性硅烷基气体和气态氧化剂形成的电介质层。 多组分层可以沉积在冷壁或热壁化学气相沉积（CVD）反应器中，并且在存在或不存在等离子体的情况下。 多组分层也可以使用诸如辐射能或快速热CVD的其它过程进行沉积。

公开(公告)号：US5358894A

公开(公告)日：1994-10-25

申请号：US175481

申请日：1993-12-30

申请人： Pierre Fazan ,  Viju Mathews ,  Gurtej S. Sandhu ,  Mohammed Anjum ,  Hiang C. Chan

发明人： Pierre Fazan ,  Viju Mathews ,  Gurtej S. Sandhu ,  Mohammed Anjum ,  Hiang C. Chan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S148/116 ,  Y10S148/163

摘要： A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.

摘要翻译： 通过在具有窄场氧化物宽度的区域中增强场氧化物来增强LOCOS工艺。 在形成氮化物图案以限定场氧化物和有源区域之后，将光致抗蚀剂施加到晶片的选定区域。 然后在不受光致抗蚀剂和氮化物保护的区域中将杂质施加到下面的半导体衬底。 杂质导致增强的氧化速率，因此补偿了选择的场氧化物区域（例如具有窄宽度的区域）中的稀化效应。 随后形成场氧化物导致掺杂材料被氧化物消耗。

公开(公告)号：US5236860A

公开(公告)日：1993-08-17

申请号：US799461

申请日：1991-11-26

申请人： Pierre Fazan ,  Gurtej S. Sandhu ,  Hiang C. Chan ,  Yauh-Ching Liu

发明人： Pierre Fazan ,  Gurtej S. Sandhu ,  Hiang C. Chan ,  Yauh-Ching Liu

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A lateral extension stacked capacitor (LESC) using a modified stacked capacitor storage cell fabrication process. The LESC is made up of polysilicon structure, having a spherical ended v-shaped cross-section. The storage node plate of the LESC is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

摘要翻译： 一种侧向延伸堆叠电容器（LESC），采用改进的堆叠电容器存储单元制造工艺。 LESC由多晶硅结构组成，具有球形末端的V形横截面。 LESC的存储节点板由介质夹在其间的多晶硅覆盖，并通过埋入触点连接到接入设备的有源区。 板延伸到相邻的存储节点，但是通过小于给定光刻技术的临界分辨率尺寸与相邻节点隔离。 多晶硅结构的添加增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器电池定义的表面积。

公开(公告)号：US06573182B2

公开(公告)日：2003-06-03

申请号：US09961909

申请日：2001-09-24

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： H01L2144

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L27/10852

摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

公开(公告)号：US06674169B2

公开(公告)日：2004-01-06

申请号：US09962003

申请日：2001-09-24

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： H01L2348

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L27/10852

摘要： A semiconductor device comprised of a substantially conformal layer of titanium silicon oxide deposited on a semiconductor substrate. The layer of titanium silicon oxide is substantially free of chlorine related impurities. The layer of titanium silicon oxide may have a ratio of silicon to titanium from about 0.1 to about 1.9. The layer of titanium silicon oxide may have a dielectric constant from about 10 to about 30, and a thickness from about 15 angstroms to about 500 angstroms.

摘要翻译： 一种半导体器件，包括沉积在半导体衬底上的基本上保形的氧化钛硅层。 钛氧化硅层基本上不含氯相关杂质。 钛硅氧化物层可以具有约0.1至约1.9的硅与钛的比例。 钛氧化硅层可以具有约10至约30的介电常数和约15埃至约500埃的厚度。

公开(公告)号：US06313035B1

公开(公告)日：2001-11-06

申请号：US08660059

申请日：1996-05-31

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： H01L2144

CPC分类号： H01L21/31604 ,  C23C16/40 ,  H01L27/10852

摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

摘要翻译： 在半导体工艺中在半导体衬底上沉积多组分层。 多组分层可以是由气态钛有机金属前体，反应性硅烷基气体和气态氧化剂形成的电介质层。 多组分层可以沉积在冷壁或热壁化学气相沉积（CVD）反应器中，并且存在或不存在等离子体。 多组分层也可以使用诸如辐射能或快速热CVD的其它过程进行沉积。

公开(公告)号：US5156987A

公开(公告)日：1992-10-20

申请号：US812234

申请日：1991-12-18

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/2022 ,  H01L21/8221 ,  H01L29/78654 ,  Y10S148/109

摘要： The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.

摘要翻译： 本发明引入一种制造具有外延生长沟道区域的有源PMOS薄膜晶体管（或p-ch TFT）的方法，用于高性能操作特性。 通常，这种p-ch TFT器件将被制造成覆盖在NMOS有源器件上，从而变成所使用的NMOS器件的有源负载（或上拉），这样的应用是在静态随机存取存储器（SRAM）中创建存储器单元。 如果需要，可以互换电导型（p型或n型）以构造与PMOS有源器件耦合的n沟道TFT。 本发明的TFT的制造可以用于形成CMOS反相器，或者当集成到常规CMOS制造工艺中时，可以简单地形成有源上拉器件。

公开(公告)号：US5187638A

公开(公告)日：1993-02-16

申请号：US919671

申请日：1992-07-27

申请人： Gurtej S. Sandhu ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Pierre Fazan

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L27/108 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L27/11502 ,  H01L27/10808 ,  H01L28/75 ,  H01L21/28568 ,  H01L28/55

摘要： The present invention introduces an effective way to produce a thin film capacitor utilizing a high dielectric constant material for the cell dielectric through the use of a single transition metal, such as Molybdenum, for a bottom plate electrode which oxidizes to form a highly conducting oxide. Using Molybdenum, for example, will make a low resistive contact to the underlying silicon since Molybdenum reacts with silicon to form MoSix with low (

摘要翻译： 本发明通过使用单一过渡金属（例如钼）制造用于电介质的高介电常数材料的薄膜电容器用于氧化形成高导电氧化物的底板电极的有效方法。 例如，使用钼将会与下面的硅形成低电阻接触，因为钼与硅反应以形成具有低（<500μm欧姆 - 厘米）体积电阻的MoSix。 此外，Mo / MoSix与现在的ULSI工艺流程兼容或者制造DRAM等。

公开(公告)号：US5130885A

公开(公告)日：1992-07-14

申请号：US727701

申请日：1991-07-10

申请人： Pierre Fazan ,  Gurtej S. Sandhu

发明人： Pierre Fazan ,  Gurtej S. Sandhu

IPC分类号： H01L27/108

CPC分类号： H01L27/10808

摘要： A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.

摘要翻译： 具有粗糙表面形态的硅 - 锗合金层用于电池电容器的存储节点板的电容表面的动态随机存取存储单元。 为了形成具有这样的单元的DRAM阵列，通常通过快速热化学气相沉积在单晶硅或多晶硅存储节点板层的顶部上沉积硅 - 锗合金，在有利于三维生长的条件下 宏观孤岛的形式（即前体气体中的锗浓度高，沉积温度较高）。 利用表现出体积受限的传导特性（例如，氮化硅）的电介质层。 除了硅锗合金的沉积之外，阵列加工是常规的。