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    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same
    1.
    发明授权
    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same 有权
    包括具有抗穿透杂质区域的选择晶体管的NAND型闪存器件及其制造方法

    公开(公告)号：US07683421B2

    公开(公告)日：2010-03-23

    申请号：US11849533

    申请日：2007-09-04

    申请人： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    发明人： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    IPC分类号： H01L29/10

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/1083 ,  H01L29/78

    摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.

    摘要翻译： 提供了包括选择晶体管的NAND型闪速存储器件。 该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。 第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。 多个单元栅极图案设置在第一和第二选择栅极图案之间。 在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。 第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。 在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。 第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

    NAND-TYPE FLASH MEMORY DEVICES INCLUDING SELECTION TRANSISTORS WITH AN ANTI-PUNCHTHROUGH IMPURITY REGION AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    NAND-TYPE FLASH MEMORY DEVICES INCLUDING SELECTION TRANSISTORS WITH AN ANTI-PUNCHTHROUGH IMPURITY REGION AND METHODS OF FABRICATING THE SAME 有权
    NAND型闪存存储器件，其中包括具有防伪突变区域的选择晶体管及其制造方法

    公开(公告)号：US20080083944A1

    公开(公告)日：2008-04-10

    申请号：US11849533

    申请日：2007-09-04

    申请人： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    发明人： Gyoung-Ho Buh ,  Sun-Ghil Lee ,  Jong-Ryeol Yoo ,  Deok-Hyung Lee ,  Guk-Hyon Yon

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/1083 ,  H01L29/78

    摘要： A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.

    摘要翻译： 提供了包括选择晶体管的NAND型闪速存储器件。 该器件包括形成在半导体衬底中的第一和第二杂质区，以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。 第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。 多个单元栅极图案设置在第一和第二选择栅极图案之间。 在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。 第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。 在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。 第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

    Semiconductor device including carrier accumulation layers
    3.
    发明授权
    Semiconductor device including carrier accumulation layers 失效
    半导体器件包括载流子堆积层

    公开(公告)号：US07514744B2

    公开(公告)日：2009-04-07

    申请号：US11322335

    申请日：2005-12-30

    申请人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

    发明人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

    摘要翻译： 半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。 该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。 与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。 表面绝缘层与源极/漏极区之间的界面包括多个界面状态。 紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。 载体积聚层沿着间隔物下的界面延伸。 还讨论了相关方法。

    Method of increasing a free carrier concentration in a semiconductor substrate
    8.
    发明授权
    Method of increasing a free carrier concentration in a semiconductor substrate 失效
    增加半导体衬底中自由载流子浓度的方法

    公开(公告)号：US07485554B2

    公开(公告)日：2009-02-03

    申请号：US11655916

    申请日：2007-01-22

    申请人： Gyoung Ho Buh ,  Ji-Sang Yahng ,  Yu Gyun Shin ,  Guk-Hyon Yon ,  Sangjin Hyun

    发明人： Gyoung Ho Buh ,  Ji-Sang Yahng ,  Yu Gyun Shin ,  Guk-Hyon Yon ,  Sangjin Hyun

    IPC分类号： H01L21/26 ,  H01L21/42

    CPC分类号： H01L21/266 ,  H01L21/2022 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/28211 ,  H01L21/324 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481

    摘要： A method of selectively heating a predetermined region of a semiconductor substrate includes providing a semiconductor substrate, selectively focusing a free carrier generation light on only a predetermined region of the semiconductor substrate, irradiating the free carrier generation light on the predetermined region of the semiconductor substrate to increase a free carrier concentration within the predetermined region of the semiconductor substrate, wherein the free carrier generation light causes the predetermined region to increase in temperature by less than a temperature necessary to change the solid phase of the predetermined region, and irradiating the semiconductor substrate with a heating light to selectively heat the predetermined region of the semiconductor substrate.

    摘要翻译： 选择性地加热半导体衬底的预定区域的方法包括提供半导体衬底，将仅自由载流子产生光选择性地聚焦在半导体衬底的预定区域上，将半导体衬底的预定区域上的自由载流子产生光照射到 增加半导体衬底的预定区域内的自由载流子浓度，其中自由载流子产生光使预定区域的温度升高小于改变预定区域的固相所需的温度，并且将半导体衬底照射 加热光，以选择性地加热半导体衬底的预定区域。

    Semiconductor devices including carrier accumulation layers and methods for fabricating the same
    10.
    发明申请
    Semiconductor devices including carrier accumulation layers and methods for fabricating the same 失效
    包括载体积聚层的半导体器件及其制造方法

    公开(公告)号：US20060145254A1

    公开(公告)日：2006-07-06

    申请号：US11322335

    申请日：2005-12-30

    申请人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

    发明人： Gyoung-Ho Buh ,  Yu-Gyun Shin ,  Soo-Jin Hong ,  Guk-Hyon Yon

    IPC分类号： H01L29/76

    CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.

    摘要翻译： 半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。 该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。 与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。 表面绝缘层与源极/漏极区之间的界面包括多个界面状态。 紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。 载体积聚层沿着间隔物下的界面延伸。 还讨论了相关方法。