摘要:
A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.
摘要:
A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.
摘要:
Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode extending in a second direction crossing the first direction, and provided on a top surface and side surfaces of the stepped portion of the fin.
摘要:
A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.
摘要:
A FinFET may include a semiconductor fin having a top surface and a sidewall having different crystal planes. A gate dielectric layer on the top surface and on the sidewall has different thicknesses. A gate electrode is formed on the gate dielectric layer across the top surface and sidewall of the semiconductor fin.
摘要:
A method for forming a semiconductor device includes forming at least one gate electrode having a bent structure along a first direction on a semiconductor substrate, the gate electrode having first and second vertical portions, forming at least one semiconductor fin along a second direction on the semiconductor substrate, the semiconductor fin positioned between the first and second vertical portions of the gate electrode, forming a first epitaxial layer on the semiconductor fin, the first epitaxial layer including a source/drain impurity region, and forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a contact impurity region.
摘要:
Methods of forming an integrated circuit memory device include forming a dielectric layer on a substrate and forming a charge storing layer on an upper surface of the dielectric layer using a plasma doping process with a remaining portion of the dielectric layer under the charge storing layer defining a tunnel dielectric layer. A blocking dielectric layer is formed on the charge storing layer and a gate electrode layer is formed on the blocking dielectric layer.
摘要:
A method of forming an oxide layer on a trench, a method of forming a semiconductor device, and a semiconductor device, the method of forming an oxide layer on a trench including forming a first trench in a first portion of a substrate and a second trench in a second portion of the substrate, the first portion being different from the second portion, performing a plasma doping process on at least one of the first portion and the second portion to implant an impurity therein, and performing an oxidation process to form an oxide layer on the substrate, a thickness of the oxide layer being determined by the impurity implanted in the substrate.
摘要:
Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.
摘要:
Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.