NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same
    1.
    发明授权
    NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same 有权
    包括具有抗穿透杂质区域的选择晶体管的NAND型闪存器件及其制造方法

    公开(公告)号:US07683421B2

    公开(公告)日:2010-03-23

    申请号:US11849533

    申请日:2007-09-04

    IPC分类号: H01L29/10

    摘要: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.

    摘要翻译: 提供了包括选择晶体管的NAND型闪速存储器件。 该器件包括形成在半导体衬底中的第一和第二杂质区,以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。 第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。 多个单元栅极图案设置在第一和第二选择栅极图案之间。 在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。 第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。 在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。 第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

    NAND-TYPE FLASH MEMORY DEVICES INCLUDING SELECTION TRANSISTORS WITH AN ANTI-PUNCHTHROUGH IMPURITY REGION AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    NAND-TYPE FLASH MEMORY DEVICES INCLUDING SELECTION TRANSISTORS WITH AN ANTI-PUNCHTHROUGH IMPURITY REGION AND METHODS OF FABRICATING THE SAME 有权
    NAND型闪存存储器件,其中包括具有防伪突变区域的选择晶体管及其制造方法

    公开(公告)号:US20080083944A1

    公开(公告)日:2008-04-10

    申请号:US11849533

    申请日:2007-09-04

    IPC分类号: H01L29/78 H01L21/336

    摘要: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate. The second anti-punchthrough impurity region overlaps with a first edge of the second selection gate pattern adjacent to the second impurity region.

    摘要翻译: 提供了包括选择晶体管的NAND型闪速存储器件。 该器件包括形成在半导体衬底中的第一和第二杂质区,以及设置在第一和第二杂质区之间的半导体衬底上的第一和第二选择栅极图案。 第一和第二选择栅极图案分别与第一和第二杂质区相邻设置。 多个单元栅极图案设置在第一和第二选择栅极图案之间。 在半导体衬底中设置围绕第一杂质区的第一抗穿透杂质区。 第一抗穿透杂质区域与第一选择栅极图案的与第一杂质区域相邻的第一边缘重叠。 在半导体衬底中设置有围绕第二杂质区的第二抗穿透杂质区。 第二抗穿透杂质区域与第二选择栅极图案的与第二杂质区域相邻的第一边缘重叠。

    Semiconductor device and method for formimg the same
    6.
    发明申请
    Semiconductor device and method for formimg the same 审中-公开
    半导体器件和方法相同

    公开(公告)号:US20080073730A1

    公开(公告)日:2008-03-27

    申请号:US11902404

    申请日:2007-09-21

    IPC分类号: H01L29/78 H01L21/336

    摘要: A method for forming a semiconductor device includes forming at least one gate electrode having a bent structure along a first direction on a semiconductor substrate, the gate electrode having first and second vertical portions, forming at least one semiconductor fin along a second direction on the semiconductor substrate, the semiconductor fin positioned between the first and second vertical portions of the gate electrode, forming a first epitaxial layer on the semiconductor fin, the first epitaxial layer including a source/drain impurity region, and forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including a contact impurity region.

    摘要翻译: 一种形成半导体器件的方法包括:在半导体衬底上沿着第一方向形成具有弯曲结构的至少一个栅电极,所述栅极具有第一和第二垂直部分,在半导体上沿着第二方向形成至少一个半导体鳍片 衬底,所述半导体鳍片位于所述栅电极的所述第一和第二垂直部分之间,在所述半导体鳍片上形成第一外延层,所述第一外延层包括源/漏杂质区,以及在所述第一外延层上形成第二外延层 层,第二外延层包括接触杂质区。

    Method of forming oxide layer, and method of manufacturing semiconductor device
    8.
    发明申请
    Method of forming oxide layer, and method of manufacturing semiconductor device 审中-公开
    形成氧化物层的方法和制造半导体器件的方法

    公开(公告)号:US20100055856A1

    公开(公告)日:2010-03-04

    申请号:US12461896

    申请日:2009-08-27

    IPC分类号: H01L21/8242 H01L21/31

    摘要: A method of forming an oxide layer on a trench, a method of forming a semiconductor device, and a semiconductor device, the method of forming an oxide layer on a trench including forming a first trench in a first portion of a substrate and a second trench in a second portion of the substrate, the first portion being different from the second portion, performing a plasma doping process on at least one of the first portion and the second portion to implant an impurity therein, and performing an oxidation process to form an oxide layer on the substrate, a thickness of the oxide layer being determined by the impurity implanted in the substrate.

    摘要翻译: 在沟槽上形成氧化物层的方法,形成半导体器件的方法和半导体器件,在沟槽上形成氧化物层的方法,包括在衬底的第一部分中形成第一沟槽和第二沟槽 在所述衬底的第二部分中,所述第一部分与所述第二部分不同,在所述第一部分和所述第二部分中的至少一个上执行等离子体掺杂工艺以在其中注入杂质,并进行氧化处理以形成氧化物 层,该氧化物层的厚度由注入衬底中的杂质决定。