公开(公告)号：US20170196113A1

公开(公告)日：2017-07-06

申请号：US15315380

申请日：2014-07-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John NORTON ,  Melvin K BENEDICT ,  John P FRANZ

IPC: H05K7/14 ,  H01R12/73 ,  H01R13/629 ,  H05K7/20

CPC classification number: H05K7/1431 ,  H01R12/73 ,  H01R13/629 ,  H01R2201/06 ,  H05K7/20418

Abstract: A dual in-line memory module (DIMM) connector can include a double data rate fourth generation (DDR4) DIMM connector to connect to a DIMM via a lowest notch of the DIMM relative to an electronic component on which the DIMM is located.

公开(公告)号：US20190026026A1

公开(公告)日：2019-01-24

申请号：US15752250

申请日：2015-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K BENEDICT ,  Eric L POPE

IPC: G06F3/06

Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

公开(公告)号：US20160357233A1

公开(公告)日：2016-12-08

申请号：US15120511

申请日：2014-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thomas Robert BOWDEN ,  Allen B DOERR ,  John FRANZ ,  Melvin K BENEDICT ,  Joseph ALLEN ,  John NORTON ,  Binh NGUYEN

IPC: G06F1/20 ,  G06F13/42

CPC classification number: G06F1/206 ,  G06F1/185 ,  G06F1/20 ,  G06F13/42 ,  H01L23/367 ,  H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.

Abstract translation: 根据一个示例的热管理组件可以包括第一热管理构件，其包括连续的第一主区域，不连续的第一连接区域和第一顶侧面。 热管理组件还可以包括第二热管理构件，其包括第二主区域，第二连接区域和第二顶侧。 第二主区域和第二连接区域是连续的。 热管理组件还可以包括连接构件，用于经由第一连接区域和第二连接区域将第一热管理构件和第二热管理构件连接到存储装置。 当第一热管理构件和第二热管理构件联接到存储装置时，第一顶侧和第二顶侧基本上与存储装置的顶侧在水平方向平齐。

公开(公告)号：US20160336047A1

公开(公告)日：2016-11-17

申请号：US15112995

申请日：2014-01-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K BENEDICT ,  Karl J BOIS ,  Stephen F CONTRERAS ,  Mark FRANK

IPC: G11C5/06 ,  H01L23/498 ,  H01L23/50

CPC classification number: G11C5/063 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0251 ,  H05K1/0253 ,  H01L2924/00

Abstract: A system can include a memory circuit having a first signal via, a first signal return via, and at least one second signal return via located closer to the control signal via than the first signal return via.

Abstract translation: 系统可以包括具有第一信号通路，第一信号返回通道以及位于比第一信号返回通路更靠近控制信号通路的至少一个第二信号返回通道的存储器电路。

公开(公告)号：US20180322052A1

公开(公告)日：2018-11-08

申请号：US15775390

申请日：2016-02-19

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K BENEDICT

IPC: G06F12/0804 ,  G06F12/0866 ,  G06F12/123 ,  G06F12/1009

CPC classification number: G06F12/0804 ,  G06F11/30 ,  G06F11/3037 ,  G06F11/3423 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/123 ,  G06F2201/885 ,  G06F2212/2022 ,  G06F2212/222

Abstract: Various examples described herein provide for deferred write back based on age time. According to some examples, an age time for a cached instance stored on a data cache is monitored and, based on the age time, a cache table entry for the cached instance may be modified to indicate that the cached instance is a candidate for a deferred write back period. A controller may monitor for a deferred write back period based on data activity of the data cache. During a deferred write back period, the cached instance may be written back from volatile memory to the non-volatile memory based on whether the cache table entry indicates that the cached instance has been modified and based on whether the cache table entry indicates that the cached instance is a candidate for the deferred write back period.

公开(公告)号：US20180301183A1

公开(公告)日：2018-10-18

申请号：US15768536

申请日：2015-10-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M BACCHUS ,  Melvin K BENEDICT ,  Eric L POPE

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4076 ,  G11C7/20

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

公开(公告)号：US20180293189A1

公开(公告)日：2018-10-11

申请号：US15766367

申请日：2015-10-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M BACCHUS ,  Melvin K BENEDICT ,  Eric L POPE

IPC: G06F13/16 ,  G06F12/02 ,  G06F9/30

Abstract: A memory device includes a memory storage media to store data for the memory device. A memory manager initiates an autonomous precharge of a buffered page into the memory storage media in the absence of detecting a command at an input of the memory device for a period of time that exceeds a threshold.