公开(公告)号：US20160196077A9

公开(公告)日：2016-07-07

申请号：US14492107

申请日：2014-09-22

Applicant: Hitachi, Ltd.

Inventor： Shuji NAKAMURA ,  Akira FUJIBAYASHI ,  Mutsumi HOSOYA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0676 ,  G06F3/0689 ,  H04L49/357 ,  H04L67/1002 ,  H04L67/1097 ,  H04L69/08

Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.

Abstract translation: 存储系统：其中处理器号信息包括至少一个逻辑单元号和至少一个处理器数量的存储节点; 其中传送列表索引/处理器号信息包括用于从多个存储节点的处理器中识别处理器的处理器号，以及用于识别包括处理器发送给协议处理器的指令的传送列表的索引信息; 其中本地路由器响应于来自主计算机的协议处理器的写入请求，基于处理器号信息从多个存储节点的处理器中确定作为写请求的传送目的地的第一处理器; 其中所述第一处理器生成并向所述协议处理器发送包括用于处理的指令的第一传送列表，并且在接收到所述写入请求时生成作为所述第一传送列表的索引的第一索引信息。

公开(公告)号：US20160179380A1

公开(公告)日：2016-06-23

申请号：US14989965

申请日：2016-01-07

Applicant: Hitachi, Ltd.

Inventor： Shuji NAKAMURA ,  Kazuhisa FUJIMOTO ,  Akira FUJIBAYASHI

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/061 ,  G06F3/0626 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0866 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/263 ,  G06F2212/314 ,  G06F2212/60 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/26 ,  Y02D10/13

Abstract: A system includes a plurality of flash memory devices, a processor configured to control read/write requests, and a cache memory configured to store data temporarily. The processor is configured to, according to a read request for first data from a read/write data source, when the first data is not stored within the cache memory, transfer the first data requested by the read request from one of the plurality of flash memory devices to the read/write data source without storing the first data in the cache memory, and according to a write request from the read/write data source, store second data requested by the write request in the cache memory

Abstract translation: 一种系统包括多个闪存器件，被配置为控制读/写请求的处理器，以及被配置为临时存储数据的高速缓存存储器。 所述处理器被配置为：当所述第一数据未被存储在所述高速缓冲存储器内时，根据对来自读/写数据源的第一数据的读取请求，将所述读请求所请求的所述第一数据从所述多个闪存 存储器件到读/写数据源，而不将第一数据存储在高速缓冲存储器中，并且根据来自读/写数据源的写请求，将写请求所请求的第二数据存储在高速缓冲存储器

公开(公告)号：US20160085463A1

公开(公告)日：2016-03-24

申请号：US14492107

申请日：2014-09-22

Applicant: Hitachi, Ltd.

Inventor： Shuji NAKAMURA ,  Akira FUJIBAYASHI ,  Mutsumi HOSOYA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0676 ,  G06F3/0689 ,  H04L49/357 ,  H04L67/1002 ,  H04L67/1097 ,  H04L69/08

Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.

公开(公告)号：US20140095776A1

公开(公告)日：2014-04-03

申请号：US14098575

申请日：2013-12-06

Applicant: HITACHI, LTD.

Inventor： Shuji NAKAMURA ,  Kazuhisa FUJIMOTO ,  Akira FUJIBAYASHI

IPC: G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0626 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0866 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/263 ,  G06F2212/314 ,  G06F2212/60 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/26 ,  Y02D10/13

Abstract: A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller.

Abstract translation: 一种存储系统，包括存储装置，其包括用于存储来自主计算机的数据的介质，用于控制所述介质的介质控制器，用于通过信道连接到所述主计算机的多个通道控制器，以及用于临时存储来自所述主机的数据的高速缓存存储器 主机，其中媒体对多个写入时间具有限制。 存储装置包括用于将数据从介质控制器直接传送到信道控制器的总线。

公开(公告)号：US20130238845A1

公开(公告)日：2013-09-12

申请号：US13867155

申请日：2013-04-22

Applicant: HITACHI, LTD.

Inventor： Masayuki YAMAMOTO ,  Akira YAMAMOTO ,  Akira FUJIBAYASHI ,  Jun KITAHARA ,  Yoshiki KANO

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/0616 ,  G06F3/0644 ,  G06F3/0685 ,  G06F2212/1036 ,  G06F2212/7206

Abstract: For a storage apparatus where flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. The storage apparatus includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. The storage controller can form a storage area using a flash memory or a magnetic disk to create a logical volume. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions on the number deletions of the flash memory.

Abstract translation: 对于闪存盘和硬盘共存的存储装置，实现了高密度安装闪存模块。 存储装置包括闪存和存储控制器。 包括磁盘的第二存储装置连接到存储装置。 存储控制器可以使用闪存或磁盘形成存储区域以创建逻辑卷。 当从主计算机发出输入/输出请求时，如果存储区域形成闪速存储器，则存储控制器直接访问闪存以处理该请求。 当存储装置定义形成有闪速存储器的存储区域时，存储装置通过将要提供给主计算机的存储区域的容量相加来确定存储区域，并且考虑到对数量的限制而确定的替代区域容量 闪存的删除。

公开(公告)号：US20130086314A1

公开(公告)日：2013-04-04

申请号：US13688447

申请日：2012-11-29

Applicant: Hitachi, Ltd.

Inventor： Shuji NAKAMURA ,  Kazuhisa FUJIMOTO ,  Akira FUJIBAYASHI

IPC: G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0626 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/067 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0866 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/263 ,  G06F2212/314 ,  G06F2212/60 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/26 ,  Y02D10/13

Abstract: A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller.