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    Integrated circuit chip and transmitting /receiving system including the same
    1.
    发明授权
    Integrated circuit chip and transmitting /receiving system including the same 有权
    集成电路芯片和发送/接收系统包括相同的

    公开(公告)号：US08633762B2

    公开(公告)日：2014-01-21

    申请号：US13333692

    申请日：2011-12-21

    申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC分类号： H01L25/00

    CPC分类号： G06F13/4077

    摘要： A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

    摘要翻译： 用于发送数据的系统包括被配置为发送数据的多条数据线和被配置为将数据输出到数据线的发送芯片，并且响应于要通过数据发送的数据的数据模式执行串扰防止操作 数据线的线和阵列信息，以防止在数据线中发生串扰。

    Input buffer circuit of semiconductor apparatus
    2.
    发明授权
    Input buffer circuit of semiconductor apparatus 有权
    半导体装置的输入缓冲电路

    公开(公告)号：US08339159B2

    公开(公告)日：2012-12-25

    申请号：US12540496

    申请日：2009-08-13

    申请人： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153

    摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

    摘要翻译： 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

    Voltage regulator for a synchronous clock system to reduce clock tree jitter
    3.
    发明授权
    Voltage regulator for a synchronous clock system to reduce clock tree jitter 失效
    用于同步时钟系统的电压调节器，以减少时钟树抖动

    公开(公告)号：US08026701B2

    公开(公告)日：2011-09-27

    申请号：US12265908

    申请日：2008-11-06

    申请人： Hyung-Soo Kim ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Hyung-Soo Kim ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： G05F1/652

    CPC分类号： G11C5/147

    摘要： A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

    摘要翻译： 具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。 第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。 电压产生单元基于参考电压产生调节电压。 微调电容器单元控制电压产生单元的负载电容。 第二缓冲链使用调节电压作为电源电压来延迟时钟信号。 控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。

    Duty cycle correction circuit with reduced current consumption
    8.
    发明授权
    Duty cycle correction circuit with reduced current consumption 失效
    占空比校正电路，降低电流消耗

    公开(公告)号：US07786783B2

    公开(公告)日：2010-08-31

    申请号：US12333193

    申请日：2008-12-11

    申请人： Hee-Woong Song ,  Yong-Ju Kim ,  Sung-Woo Han ,  Jae-Min Jang ,  Hyung-Soo Kim ,  Ji-Wang Lee ,  Chang-Kun Park ,  Ic-Su Oh ,  Hae-Rang Choi ,  Tae-Jin Hwang

    发明人： Hee-Woong Song ,  Yong-Ju Kim ,  Sung-Woo Han ,  Jae-Min Jang ,  Hyung-Soo Kim ,  Ji-Wang Lee ,  Chang-Kun Park ,  Ic-Su Oh ,  Hae-Rang Choi ,  Tae-Jin Hwang

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

    摘要翻译： 一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到 所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平 输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

    Semiconductor integrated circuit and method for driving the same
    10.
    发明授权
    Semiconductor integrated circuit and method for driving the same 有权
    半导体集成电路及其驱动方法

    公开(公告)号：US08542044B2

    公开(公告)日：2013-09-24

    申请号：US13334241

    申请日：2011-12-22

    申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

    摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

    摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。