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69 条记录 (耗时 0.033 秒)

    MAJORITY DECISION CIRCUIT
    1.
    发明申请
    MAJORITY DECISION CIRCUIT 有权
    重大决策电路

    公开(公告)号：US20130113518A1

    公开(公告)日：2013-05-09

    申请号：US13334355

    申请日：2011-12-22

    申请人： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    发明人： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

    IPC分类号： H03K19/23

    CPC分类号： H03K19/0813 ,  H03K19/23

    摘要： A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

    摘要翻译： 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段

    Semiconductor integrated circuit and method for driving the same
    3.
    发明授权
    Semiconductor integrated circuit and method for driving the same 有权
    半导体集成电路及其驱动方法

    公开(公告)号：US08542044B2

    公开(公告)日：2013-09-24

    申请号：US13334241

    申请日：2011-12-22

    申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

    摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

    摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

    Low power variable delay circuit
    5.
    发明授权
    Low power variable delay circuit 有权
    低功率可变延迟电路

    公开(公告)号：US08278981B2

    公开(公告)日：2012-10-02

    申请号：US12636901

    申请日：2009-12-14

    申请人： Hae-Rang Choi ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Hae-Rang Choi ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： H03L7/00

    CPC分类号： G11C19/28

    摘要： A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

    摘要翻译： 可变延迟电路至少包括固定延迟单元，第一选择单元和可变延迟单元。 固定延迟单元接收表示第一延迟的输入信号和第一延迟选择信号，并且输出基本上延迟了第一延迟的输入信号的第一延迟信号。 第一选择单元接收输入信号，第一延迟信号和第二延迟选择信号，并且基于第二延迟选择信号将输入信号或第一延迟信号输出到可变延迟单元。 可变延迟单元还接收表示第三延迟的第三延迟选择信号，并且输出基本上延迟了第三延迟的选择单元的输出信号的输出信号。 第一个延迟是M个延迟单位的0或X倍。 第三延迟是从0到N个延迟单元中选择的延迟。

    Data relay apparatus and semiconductor integrated circuit having the same
    6.
    发明授权
    Data relay apparatus and semiconductor integrated circuit having the same 失效
    数据中继装置及具有该数据中继装置的半导体集成电路

    公开(公告)号：US08139703B2

    公开(公告)日：2012-03-20

    申请号：US12038616

    申请日：2008-02-27

    申请人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： H03D3/24

    CPC分类号： H03K5/135 ,  H03L7/06

    摘要： A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.

    摘要翻译： 根据本文所述的一个实施例的数据中继装置可以包括相位检测单元，其可以检测从发送器输出的时钟与从接收器输出的时钟之间的相位差，并且生成多个相位检测信号，数据中继控制 单元，其可以响应于所述多个相位检测信号来区分发射机和接收机的时钟之间的时钟定时的差异，并且输出中继数据选择信号和中继控制时钟，以及可以发送数据的数据中继单元 响应于继电器数据选择信号和继电器控制时钟从接收器输出到发送器。

    VOLTAGE REGULATOR
    10.
    发明申请
    VOLTAGE REGULATOR 失效
    电压稳压器

    公开(公告)号：US20090267579A1

    公开(公告)日：2009-10-29

    申请号：US12265908

    申请日：2008-11-06

    申请人： Hyung-Soo KIM ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Hyung-Soo KIM ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： G05F1/00

    CPC分类号： G11C5/147

    摘要： A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

    摘要翻译： 具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。 第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。 电压产生单元基于参考电压产生调节电压。 微调电容器单元控制电压产生单元的负载电容。 第二缓冲链使用调节电压作为电源电压来延迟时钟信号。 控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。