公开(公告)号：US07924353B2

公开(公告)日：2011-04-12

申请号：US12168165

申请日：2008-07-07

Applicant: Hsin-Ming Liao ,  Kuo-Yu Huang ,  Han-Tu Lin

Inventor： Hsin-Ming Liao ,  Kuo-Yu Huang ,  Han-Tu Lin

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F2201/40 ,  H01L27/1255

Abstract: A pixel structure is disposed on a substrate and electrically connected to a scan line and a data line. The pixel structure including an active device, a bottom capacitor electrode, an insulator, and a pixel electrode is provided. The active device is disposed on the substrate and has a gate, a source and a drain. Besides, the active device is electrically connected to the scan line and the data line. The bottom capacitor electrode and the gate are separately disposed on the substrate. The insulator covering the active device and the bottom capacitor electrode is made of a mono film. The pixel electrode is electrically connected to the active device, and at least a part of the pixel electrode extends to the insulator above the bottom capacitor electrode.

Abstract translation: 像素结构设置在基板上并电连接到扫描线和数据线。 提供了包括有源器件，底部电容器电极，绝缘体和像素电极的像素结构。 有源器件设置在衬底上并具有栅极，源极和漏极。 此外，有源器件电连接到扫描线和数据线。 底部电容器电极和栅极分别设置在基板上。 覆盖有源器件和底部电容器电极的绝缘体由单膜制成。 像素电极电连接到有源器件，并且像素电极的至少一部分延伸到底部电容器电极之上的绝缘体。

公开(公告)号：US20090262269A1

公开(公告)日：2009-10-22

申请号：US12168165

申请日：2008-07-07

Applicant: Hsin-Ming Liao ,  Kuo-Yu Huang ,  Han-Tu Lin

Inventor： Hsin-Ming Liao ,  Kuo-Yu Huang ,  Han-Tu Lin

IPC: G02F1/133

CPC classification number: G02F1/136213 ,  G02F2201/40 ,  H01L27/1255

Abstract: A pixel structure is disposed on a substrate and electrically connected to a scan line and a data line. The pixel structure including an active device, a bottom capacitor electrode, an insulator, and a pixel electrode is provided. The active device is disposed on the substrate and has a gate, a source and a drain. Besides, the active device is electrically connected to the scan line and the data line. The bottom capacitor electrode and the gate are separately disposed on the substrate. The insulator covering the active device and the bottom capacitor electrode is made of a mono film. The pixel electrode is electrically connected to the active device, and at least a part of the pixel electrode extends to the insulator above the bottom capacitor electrode.

Abstract translation: 像素结构设置在基板上并电连接到扫描线和数据线。 提供了包括有源器件，底部电容器电极，绝缘体和像素电极的像素结构。 有源器件设置在衬底上并具有栅极，源极和漏极。 此外，有源器件电连接到扫描线和数据线。 底部电容器电极和栅极分别设置在基板上。 覆盖有源器件和底部电容器电极的绝缘体由单膜制成。 像素电极电连接到有源器件，并且像素电极的至少一部分延伸到底部电容器电极之上的绝缘体。

公开(公告)号：US20090047749A1

公开(公告)日：2009-02-19

申请号：US12213253

申请日：2008-06-17

Applicant: Han-Tu Lin ,  Kuo-Yu Huang

Inventor： Han-Tu Lin ,  Kuo-Yu Huang

IPC: H01L21/336 ,  H01L33/00

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/124

Abstract: A first patterned conductive layer is formed on a substrate. A dielectric layer, a semiconductor layer, a second conductive layer and a photoresist layer are formed above the first patterned conductive layer. The photoresist layer is patterned using a photomask with multiple different transparencies, and the patterned photoresist layer has at least three different thicknesses. The photoresist layer within the channel region is removed. The second conductive layer within the channel region and part of semiconductor layer are etched to form a channel, source and drain of a thin film transistor. The photoresist layer corresponding to a pixel connecting region and a data pad region is removed to expose a pixel connecting region and a data pad. The remained photoresist layer is reflowed so as to cover the channel. The uncovered semiconductor layer is removed using the reflowed photoresist layer and the patterned second conductive layer as a mask.

Abstract translation: 在基板上形成第一图案化导电层。 在第一图案化导电层的上方形成介电层，半导体层，第二导电层和光致抗蚀剂层。 使用具有多个不同透明度的光掩模对光致抗蚀剂层进行图案化，并且图案化的光致抗蚀剂层具有至少三个不同的厚度。 去除沟道区内的光致抗蚀剂层。 沟道区域内的第二导电层和半导体层的一部分被蚀刻以形成薄膜晶体管的沟道，源极和漏极。 对应于像素连接区域和数据焊盘区域的光致抗蚀剂层被去除以暴露像素连接区域和数据焊盘。 保留的光致抗蚀剂层被回流以覆盖通道。 使用回流光致抗蚀剂层和图案化的第二导电层作为掩模去除未覆盖的半导体层。

公开(公告)号：US08071407B2

公开(公告)日：2011-12-06

申请号：US12835874

申请日：2010-07-14

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

IPC: H01L21/28

CPC classification number: H01L27/1288 ,  H01L27/124

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化 半导体层和图案化金属多层。 此外，本发明使用选择性蚀刻某些层的方法。 使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少与制造阵列基板有关的耗时且复杂的掩模蚀刻工艺的数量。 本发明提供了用于制造阵列基板的相对简单且省时的方法。

公开(公告)号：US20110284074A1

公开(公告)日：2011-11-24

申请号：US12891721

申请日：2010-09-27

Applicant: Chee-Wee Liu ,  Wei-Shuo Ho ,  Yen-Yu Chen ,  Chun-Yuan Ku ,  Chien-Jen Chen ,  Han-Tu Lin ,  Shuo-Wei Liang

Inventor： Chee-Wee Liu ,  Wei-Shuo Ho ,  Yen-Yu Chen ,  Chun-Yuan Ku ,  Chien-Jen Chen ,  Han-Tu Lin ,  Shuo-Wei Liang

IPC: H01L31/0376

CPC classification number: H01L31/0747 ,  Y02E10/50

Abstract: A photovoltaic cell includes a first type doped mono-crystalline silicon substrate, an intrinsic amorphous silicon layer, a second type doped amorphous silicon layer, a first type doped crystalline Ge-containing layer, and a pair of electrodes. The first type doped mono-crystalline silicon substrate has a front surface and a rear surface. The intrinsic amorphous silicon layer is disposed on the front surface. The second type doped amorphous silicon layer is disposed on the intrinsic amorphous silicon layer. The first type doped crystalline Ge-containing layer is disposed on the rear surface. The pair of electrodes are electrically connected to the second type doped amorphous silicon layer and first type doped crystalline Ge-containing layer, respectively.

Abstract translation: 光伏电池包括第一掺杂单晶硅衬底，本征非晶硅层，第二掺杂非晶硅层，第一掺杂晶体Ge含量层和一对电极。 第一种掺杂单晶硅衬底具有前表面和后表面。 本征非晶硅层设置在前表面上。 第二类掺杂非晶硅层设置在本征非晶硅层上。 第一类型的掺杂结晶Ge含量层设置在后表面上。 该对电极分别电连接到第二类掺杂非晶硅层和第一掺杂结晶Ge含量层。

公开(公告)号：US20110117707A1

公开(公告)日：2011-05-19

申请号：US13013887

申请日：2011-01-26

Applicant: Han-Tu Lin ,  Chien-Hung Chen

Inventor： Han-Tu Lin ,  Chien-Hung Chen

IPC: H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: A method for manufacturing a pixel structure is provided. First, a first mask process is performed to form a patterned first metal layer on a substrate, wherein the patterned first metal layer includes a gate. Next, a second mask process is performed to form a patterned insulating layer and a patterned semiconductor layer over the gate, wherein the patterned insulating layer is disposed on the patterned first metal layer, and the patterned semiconductor layer is disposed on the patterned insulating layer. Then, a third mask process is performed to define a thin film transistor (TFT) and a pixel electrode connected thereto and to form a passivation layer to cover the TFT.

Abstract translation: 提供了一种用于制造像素结构的方法。 首先，执行第一掩模处理以在基板上形成图案化的第一金属层，其中图案化的第一金属层包括栅极。 接下来，执行第二掩模处理以在栅极上形成图案化绝缘层和图案化半导体层，其中图案化绝缘层设置在图案化的第一金属层上，并且图案化的半导体层设置在图案化的绝缘层上。 然后，执行第三掩模处理以限定连接到其上的薄膜晶体管（TFT）和像素电极，并形成覆盖TFT的钝化层。

公开(公告)号：US20110012114A1

公开(公告)日：2011-01-20

申请号：US12893063

申请日：2010-09-29

Applicant: Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

Inventor： Ya-Hui Peng ,  Yi-Ya Tseng ,  Kun-Fu Huang ,  Chih-Hsien Chen ,  Han-Tu Lin

IPC: H01L29/786

CPC classification number: H01L29/66765 ,  H01L29/04 ,  H01L29/452 ,  H01L29/78678 ,  H01L29/78696

Abstract: A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 1020 atoms/cm3 and 1025 atoms/cm3. A method of fabricating a bottom-gate thin film transistor is also disclosed herein.

Abstract translation: 底栅薄膜晶体管包括栅电极，栅极绝缘层和微晶硅层。 栅电极设置在基板上。 栅极绝缘层由氮化硅构成并且设置在栅电极和基板上。 微晶硅层设置在栅极绝缘层上，对应于栅电极，其中栅极绝缘层和微晶硅层之间的接触界面具有多个氧原子，氧原子的浓度范围在1020原子之间 / cm3和1025原子/ cm3。 本文还公开了制造底栅薄膜晶体管的方法。

公开(公告)号：US20100279450A1

公开(公告)日：2010-11-04

申请号：US12835874

申请日：2010-07-14

Applicant: Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

Inventor： Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Han-Tu Lin

IPC: H01L21/28

CPC classification number: H01L27/1288 ,  H01L27/124

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 根据本发明，诸如薄膜晶体管，栅极线，栅极焊盘，数据线，数据焊盘和存储电极之类的阵列基板的元件通过形成图案化的第一金属层，绝缘层，图案化 半导体层和图案化金属多层。 此外，本发明使用选择性蚀刻某些层的方法。 使用上述方法，本发明的阵列基板具有一些具有欠切割结构的层，因此可以减少在阵列基板的制造中涉及的耗时且复杂的掩模蚀刻工艺的数量。 本发明提供了用于制造阵列基板的相对简单且省时的方法。

公开(公告)号：US07754547B2

公开(公告)日：2010-07-13

申请号：US12102027

申请日：2008-04-14

Applicant: Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

Inventor： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC: H01L21/00

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

Abstract translation: 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US20100055853A1

公开(公告)日：2010-03-04

申请号：US12617712

申请日：2009-11-12

Applicant: Chih-Chun Yang ,  Ming-Yuan Huang ,  Han-Tu Lin ,  Chih-Hung Shih ,  Ta-Wen Liao ,  Kuo-Lung Fang ,  Chia-Chi Tsai

Inventor： Chih-Chun Yang ,  Ming-Yuan Huang ,  Han-Tu Lin ,  Chih-Hung Shih ,  Ta-Wen Liao ,  Kuo-Lung Fang ,  Chia-Chi Tsai

IPC: H01L21/336

CPC classification number: H01L27/1248 ,  H01L27/1288

Abstract: A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.

Abstract translation: 提供了一种用于制造像素结构的方法。 栅极和栅极绝缘层依次形成在基板上。 半导体层和第二金属层依次形成在栅极绝缘层上。 通过使用形成在其上的图案化光致抗蚀剂层，将半导体层和第二金属层图案化以形成沟道层，源极和漏极，其中源极和漏极设置在沟道层的一部分上。 栅极，沟道，源极和漏极形成薄膜晶体管。 在图案化的光致抗蚀剂层，栅极绝缘层和薄膜晶体管上形成钝化层。 然后，去除图案化的光致抗蚀剂层，使得其上的钝化层被同时去除以形成图案化的钝化层，并且漏极被暴露。 在图案化的钝化层和漏极上形成像素电极。