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    Electrically programmable non-volatile memory cell configuration
    2.
    发明授权
    Electrically programmable non-volatile memory cell configuration 有权
    电可编程非易失性存储单元配置

    公开(公告)号：US06215140B1

    公开(公告)日：2001-04-10

    申请号：US09398691

    申请日：1999-09-20

    申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

    IPC分类号： H01L2972

    CPC分类号： H01L21/8229 ,  H01L27/1021

    摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

    摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

    Manufacturing method for a capacitor in an integrated memory circuit
    3.
    发明授权
    Manufacturing method for a capacitor in an integrated memory circuit 有权
    集成存储电路中电容器的制造方法

    公开(公告)号：US06204119B1

    公开(公告)日：2001-03-20

    申请号：US09312572

    申请日：1999-05-14

    申请人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

    发明人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

    IPC分类号： H01L218242

    CPC分类号： H01L28/87 ,  Y10S438/97

    摘要： A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

    摘要翻译： 集成存储器电路中的电容器的制造方法包括：首先将作为蚀刻停止层的第一导电层和辅助层沉积到载体上。 然后在第一导电层和辅助层的顶部上产生包含第一材料和第二材料的交替层的层序列。 层序列可以具体地具有p + / p-硅层或硅/锗层。 从层序列形成具有要制造的电容器的基极的层结构。 层结构的侧面设置有导电支撑结构。 在层结构内形成一个开口，一直到辅助层，然后除去辅助层和由第二材料制成的层。 由第一材料和支撑结构制成的层的自由表面设置有施加对电极的电容器电介质。

    Integrated electrical circuit having at least one memory cell and method for fabricating it
    4.
    发明授权
    Integrated electrical circuit having at least one memory cell and method for fabricating it 有权
    具有至少一个存储单元的集成电路及其制造方法

    公开(公告)号：US06194765B1

    公开(公告)日：2001-02-27

    申请号：US09313433

    申请日：1999-05-17

    申请人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

    发明人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

    摘要翻译： 集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。 存储单元包含彼此电连接的至少两个反相器。 反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。 根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。 互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。 本发明还涉及一种用于制造集成电路的方法。

    Bipolar transistor and method of fabricating a bipolar transistor
    6.
    发明授权
    Bipolar transistor and method of fabricating a bipolar transistor 有权
    双极晶体管和制造双极晶体管的方法

    公开(公告)号：US06867105B2

    公开(公告)日：2005-03-15

    申请号：US10215152

    申请日：2002-08-08

    申请人： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

    发明人： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

    IPC分类号： H01L21/331 ,  H01L29/732

    CPC分类号： H01L29/66287 ,  H01L29/7322

    摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

    摘要翻译： 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

    Memory device for storing electrical charge and method for fabricating the same
    7.
    发明授权
    Memory device for storing electrical charge and method for fabricating the same 失效
    用于存储电荷的存储器件及其制造方法

    公开(公告)号：US06995416B2

    公开(公告)日：2006-02-07

    申请号：US10853734

    申请日：2004-05-26

    申请人： Hans Reisinger ,  Reinhard Stengl ,  Herbert Schäfer

    发明人： Hans Reisinger ,  Reinhard Stengl ,  Herbert Schäfer

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/91 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/842 ,  Y10S977/943

    摘要： The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.

    摘要翻译： 本发明提供一种用于存储电荷的存储装置，其具有作为存储元件的施加在电极层上并连接到其上的管元件。 管元件设置有电介质涂层，用于填充管元件之间的空间的填充材料。 与填充材料连接的对电极形成为在电极层和对电极之间形成用于存储电荷的电容器。 管元件有利地包括碳纳米管，结果由于电容器电极表面的面积急剧增加，电容器的电容。

    Bipolar transistor
    9.
    发明授权
    Bipolar transistor 有权
    双极晶体管

    公开(公告)号：US07135757B2

    公开(公告)日：2006-11-14

    申请号：US10912344

    申请日：2004-08-04

    申请人： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

    发明人： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

    IPC分类号： H01L27/082

    CPC分类号： H01L29/66287 ,  H01L29/7322

    摘要： A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

    摘要翻译： 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。