公开(公告)号：US06552385B2

公开(公告)日：2003-04-22

申请号：US09756082

申请日：2001-01-08

申请人： Gerhard Beitel ,  Martin Franosch ,  Thomas Peter Haneder ,  Gerrit Lange ,  Hans Reisinger ,  Herbert Schäfer ,  Stephan Schlamminger ,  Hermann Wendt

发明人： Gerhard Beitel ,  Martin Franosch ,  Thomas Peter Haneder ,  Gerrit Lange ,  Hans Reisinger ,  Herbert Schäfer ,  Stephan Schlamminger ,  Hermann Wendt

IPC分类号： H01L27108

CPC分类号： H01L28/56 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691

摘要： A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

摘要翻译： 描述了包含BaSrTiO 3（BST）电介质的DRAM电容器。 该电介质具有能够形成电子槽的三层结构，其中电子可以永久性地被捕获。

公开(公告)号：US06548846B2

公开(公告)日：2003-04-15

申请号：US09734466

申请日：2000-12-11

申请人： Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

发明人： Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

IPC分类号： H01L27108

CPC分类号： H01L27/1085 ,  H01L27/10805

摘要： A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

摘要翻译： 用于DRAM的存储电容器具有由氮化硅构成的电介质，并且在电介质上具有彼此相对设置的至少两个电极。 对于电极，使用在材料的费米能级和电介质的导带之间具有高隧道势垒的材料。 用于电极的合适材料是金属如铂，钨和铱或硅化物。

公开(公告)号：US06204119B1

公开(公告)日：2001-03-20

申请号：US09312572

申请日：1999-05-14

申请人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

发明人： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  Y10S438/97

摘要： A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

摘要翻译： 集成存储器电路中的电容器的制造方法包括：首先将作为蚀刻停止层的第一导电层和辅助层沉积到载体上。 然后在第一导电层和辅助层的顶部上产生包含第一材料和第二材料的交替层的层序列。 层序列可以具体地具有p + / p-硅层或硅/锗层。 从层序列形成具有要制造的电容器的基极的层结构。 层结构的侧面设置有导电支撑结构。 在层结构内形成一个开口，一直到辅助层，然后除去辅助层和由第二材料制成的层。 由第一材料和支撑结构制成的层的自由表面设置有施加对电极的电容器电介质。

公开(公告)号：US06215140B1

公开(公告)日：2001-04-10

申请号：US09398691

申请日：1999-09-20

申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schäfer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC分类号： H01L2972

CPC分类号： H01L21/8229 ,  H01L27/1021

摘要： A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

摘要翻译： 提出半导体衬底中的存储单元结构，其中半导体衬底是第一导电类型。 相互平行延伸的沟槽并入半导体衬底中，并且第一地址线沿着沟槽的侧壁延伸。 第二地址线在半导体衬底上相对于沟槽横向地形成。 布置有可以改变导电性的二极管和电介质的半导体衬底区域位于第一地址线和第二地址线之间。 可以使用合适的电流脉冲来产生电介质中的击穿，由此将信息存储在电介质中。

公开(公告)号：US6022786A

公开(公告)日：2000-02-08

申请号：US32484

申请日：1998-02-27

申请人： Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

发明人： Martin Franosch ,  Wolfgang Hoenlein ,  Helmut Klose ,  Gerrit Lange ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schaefer ,  Reinhard Stengl ,  Hermann Wendt ,  Dietrich Widmann

IPC分类号： H01L21/306 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10861

摘要： For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

摘要翻译： 为了制造电容器，特别是用于动态存储单元布置，在衬底中蚀刻沟槽。 在沟槽中，产生层序列，其交替地包含掺杂的硅和含锗层的层。 通过各向异性蚀刻，半导体衬底（12）的表面暴露在沟槽底板的区域中。 沟槽填充有导电支撑结构（20）。 含锗层被选择性地去除掺杂硅层。 掺杂硅（17）和支撑结构（20）的层的暴露表面设置有电容器电介质（22），其上施加有对电极（23）。

公开(公告)号：US6127220A

公开(公告)日：2000-10-03

申请号：US312571

申请日：1999-05-14

申请人： Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

发明人： Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

摘要翻译： 在载体上施加层序列，其包含由第一导电材料和第二材料制成的交替层，其中两种材料都不同于载体材料。 在层序列中形成开口，其中填充有导电材料，从而产生中心支撑结构。 然后根据电容器的尺寸构造层序列，并且选择性地去除由第二材料制成的层，从而形成第一电容器电极。 层序列可以具有特别的p + - / p-硅层或硅/锗层。 也可以将蚀刻停止层作为最低层或第二层加入。

公开(公告)号：US6133126A

公开(公告)日：2000-10-17

申请号：US398688

申请日：1999-09-20

申请人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

发明人： Hans Reisinger ,  Martin Franosch ,  Herbert Schafer ,  Reinhard Stengl ,  Volker Lehmann ,  Gerrit Lange ,  Hermann Wendt

IPC分类号： H01L21/225 ,  H01L21/768 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/22

CPC分类号： H01L21/76888 ,  H01L21/2256 ,  H01L27/105 ,  H01L27/1052

摘要： A method for fabricating a dopant region is disclosed. The dopant region is formed by providing a semiconductor substrate that has a surface. An electrically insulating intermediate layer is applied to the surface. A doped semiconductor layer is then applied to the electrically insulating intermediate layer, the semiconductor layer being of a first conductivity type and contains a dopant of the first conductivity type. A temperature treatment of the semiconductor substrate at a predefined diffusion temperature is performed, so that the dopant diffuses partially out of the semiconductor layer through the intermediate layer into the semiconductor substrate and forms there a dopant region of the first conductivity type. The electrical conductivity of the intermediate layer is modified, so that an electrical contact between the semiconductor substrate and the semiconductor layer is produced through the intermediate layer.

摘要翻译： 公开了一种制造掺杂剂区域的方法。 通过提供具有表面的半导体衬底形成掺杂剂区域。 将电绝缘的中间层施加到表面。 然后将掺杂半导体层施加到电绝缘中间层，所述半导体层是第一导电类型并且包含第一导电类型的掺杂剂。 执行预定扩散温度下的半导体衬底的温度处理，使得掺杂剂从半导体层中部分扩散通过中间层进入半导体衬底，并在其上形成第一导电类型的掺杂区域。 改变中间层的导电性，从而通过中间层产生半导体衬底和半导体层之间的电接触。

公开(公告)号：US6117790A

公开(公告)日：2000-09-12

申请号：US302655

申请日：1999-04-30

申请人： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

发明人： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

摘要： A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

摘要翻译： 一种制造用于半导体存储器配置的电容器的方法。 在这种情况下，将可选择的可蚀刻材料施加到导电支撑件，该导电支撑件通过绝缘体层中的接触孔连接到半导体本体并且被图案化。 在其上施加第一导电层并图案化。 在第一导电层中引入一个孔，通过该孔蚀刻可选择性蚀刻的材料。 在该过程中在第一导电层下方产生空腔。 空腔的内表面和第一导电层的外表面设置有电介质层，第二导电层被施加并图案化。

公开(公告)号：US06194765B1

公开(公告)日：2001-02-27

申请号：US09313433

申请日：1999-05-17

申请人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

发明人： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

摘要翻译： 集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。 存储单元包含彼此电连接的至少两个反相器。 反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。 根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。 互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。 本发明还涉及一种用于制造集成电路的方法。

公开(公告)号：US06710388B2

公开(公告)日：2004-03-23

申请号：US09801209

申请日：2001-03-07

申请人： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

发明人： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

IPC分类号： H01L27108

CPC分类号： G11C11/22 ,  H01L29/78391

摘要： A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

摘要翻译： 适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。 第一栅极中间层包含至少一个铁电层。 除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。 第二栅极中间层包含电介质层。 第一栅电极和第二栅极通过二极管结构彼此连接。