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    Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige
    1.
    发明授权
    Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige 有权
    在制造含有奇数的器件中实现超高温（UHT）退火的方法

    公开(公告)号：US07700467B2

    公开(公告)日：2010-04-20

    申请号：US11872333

    申请日：2007-10-15

    申请人： Haowen Bu ,  Scott Gregory Bushman ,  Periannan Chidambaram

    发明人： Haowen Bu ,  Scott Gregory Bushman ,  Periannan Chidambaram

    IPC分类号： H01L21/265

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L22/12 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636

    摘要： Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

    摘要翻译： 示例性实施例提供了通过在UHT退火之前将碳并入到SiGe材料中来在硅锗（SiGe）半导体材料上实现超高温（UHT）退火的方法。 具体地，可以使用碳注入来增加SiGe材料的熔点，使得可以将超高温用于随后的退火工艺。 然后可以在UHT退火工艺期间降低晶片翘曲，并且可以减少后续工艺的潜在光刻误差。 示例性实施例还提供了一种在线控制方法，其中可以测量晶片翘曲以确定光学错误对准，从而控制制造工艺。 在各种实施例中，所公开的方法可用于制造晶体管器件的源极/漏极延伸区域和/或源极/漏极区域，和/或用于制造双极晶体管的基极区域。

    ANNEALING METHOD FOR SIGE PROCESS
    3.
    发明申请
    ANNEALING METHOD FOR SIGE PROCESS 审中-公开
    用于信号处理的退火方法

    公开(公告)号：US20090170256A1

    公开(公告)日：2009-07-02

    申请号：US12206456

    申请日：2008-09-08

    申请人： Srinivasan Chakravarthi ,  Haowen Bu ,  Periannan Chidambaram

    发明人： Srinivasan Chakravarthi ,  Haowen Bu ,  Periannan Chidambaram

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/324 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of forming a transistor comprising forming a gate structure over an n-type semiconductor body and forming recesses substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown in the recesses and a silicon cap layer is formed over the silicon germanium. Further introduction of impurities into the silicon germanium to increase the melting point thereof and implanting p-type source/drain regions in the semiconductor body is included in the method. The method concludes with performing a high temperature thermal treatment.

    摘要翻译： 一种形成晶体管的方法，包括在n型半导体本体上形成栅极结构，并形成与半导体本体中的栅极结构基本对准的凹槽。 然后在凹槽中外延生长硅锗，并在硅锗上形成硅帽层。 在该方法中包括将杂质进一步引入硅锗以增加其熔点并在半导体本体中注入p型源/漏区。 该方法的结论是进行高温热处理。

    IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR
    5.
    发明申请
    IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR 有权
    用于MOS晶体管的In-SITU碳掺杂e-SiGeCB堆叠

    公开(公告)号：US20090309140A1

    公开(公告)日：2009-12-17

    申请号：US12482896

    申请日：2009-06-11

    申请人： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

    发明人： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5'31019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.

    摘要翻译： 包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。 第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。 第二PSD层是Si-Ge，并且包括密度在5×1019原子/ cm3至2×1020原子/ cm3之间的碳和密度高于5×1019原子/ cm3的硼。 第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。 在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。 一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

    Antimony ion implantation for semiconductor components
    7.
    发明申请
    Antimony ion implantation for semiconductor components 有权
    半导体元件的锑离子注入

    公开(公告)号：US20070218662A1

    公开(公告)日：2007-09-20

    申请号：US11725927

    申请日：2007-03-20

    申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

    发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

    IPC分类号： H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

    摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

    摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

    Drive current improvement from recessed SiGe incorporation close to gate
    9.
    发明授权
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US07244654B2

    公开(公告)日：2007-07-17

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。