公开(公告)号：US20070105368A1

公开(公告)日：2007-05-10

申请号：US11268036

申请日：2005-11-07

Applicant: Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/823807 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823864

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract translation: 本发明在一个实施例中提供了一种制造微电子器件200的方法。 该实施例包括在衬底210和栅极结构230上形成衬垫310，使衬垫310经受电子束405并在衬垫310上沉积预金属介电层415。

公开(公告)号：US07939400B2

公开(公告)日：2011-05-10

申请号：US12235766

申请日：2008-09-23

Applicant: Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US20060172481A1

公开(公告)日：2006-08-03

申请号：US11049275

申请日：2005-02-02

Applicant: Ting Tsui ,  Satyavolu Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Satyavolu Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469 ,  H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US20070210421A1

公开(公告)日：2007-09-13

申请号：US11374635

申请日：2006-03-13

Applicant: Haowen Bu ,  Anand Krishnan ,  Ting Tsui ,  William Dostalik ,  Rajesh Khamankar

Inventor： Haowen Bu ,  Anand Krishnan ,  Ting Tsui ,  William Dostalik ,  Rajesh Khamankar

IPC: H01L23/58 ,  H01L21/469

CPC classification number: H01L21/02167 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.

Abstract translation: 本发明一方面提供一种制造半导体器件的方法。 一方面，该方法包括在栅电极上形成碳化物层，并在碳化物层上沉积预金属电介质层。 该方法显着降低了NBTI漂移。

公开(公告)号：US20090017588A1

公开(公告)日：2009-01-15

申请号：US12235766

申请日：2008-09-23

Applicant: Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07442597B2

公开(公告)日：2008-10-28

申请号：US11049275

申请日：2005-02-02

Applicant: Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

Abstract translation: 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US20090309140A1

公开(公告)日：2009-12-17

申请号：US12482896

申请日：2009-06-11

Applicant: Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

Inventor： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

Abstract: An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5'31019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.

Abstract translation: 包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。 第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。 第二PSD层是Si-Ge，并且包括密度在5×1019原子/ cm3至2×1020原子/ cm3之间的碳和密度高于5×1019原子/ cm3的硼。 第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。 在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。 一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

公开(公告)号：US07601575B2

公开(公告)日：2009-10-13

申请号：US11072779

申请日：2005-03-04

Applicant: Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

Inventor： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/44

CPC classification number: H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  Y10S438/902

Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

Abstract translation: 本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。 该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。 在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。 这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

公开(公告)号：US20070218662A1

公开(公告)日：2007-09-20

申请号：US11725927

申请日：2007-03-20

Applicant: Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

Inventor： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

IPC: H01L21/425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

Abstract: A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

Abstract translation: 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

公开(公告)号：US07253049B2

公开(公告)日：2007-08-07

申请号：US11017469

申请日：2004-12-20

Applicant: Jiong-Ping Lu ,  Shaofeng Yu ,  Haowen Bu ,  Lindsey H. Hall ,  Mark R. Visokay

Inventor： Jiong-Ping Lu ,  Shaofeng Yu ,  Haowen Bu ,  Lindsey H. Hall ,  Mark R. Visokay

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.

Abstract translation: 一种用于在半导体衬底20上制造PMOS和NMOS晶体管60,70的方法，其包括在源/漏硅化物120形成期间在栅电极层110上方具有栅极保护层210。 该方法可以包括在形成保护层215之前将掺杂剂注入到栅极多晶硅层115中。