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    IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR
    1.
    发明申请
    IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR 有权
    用于MOS晶体管的In-SITU碳掺杂e-SiGeCB堆叠

    公开(公告)号：US20090309140A1

    公开(公告)日：2009-12-17

    申请号：US12482896

    申请日：2009-06-11

    申请人： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

    发明人： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5'31019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.

    摘要翻译： 包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。 第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。 第二PSD层是Si-Ge，并且包括密度在5×1019原子/ cm3至2×1020原子/ cm3之间的碳和密度高于5×1019原子/ cm3的硼。 第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。 在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。 一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

    In-situ carbon doped e-SiGeCB stack for MOS transistor
    2.
    发明授权
    In-situ carbon doped e-SiGeCB stack for MOS transistor 有权
    用于MOS晶体管的原位碳掺杂e-SiGeCB堆叠

    公开(公告)号：US08471307B2

    公开(公告)日：2013-06-25

    申请号：US12482896

    申请日：2009-06-11

    申请人： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

    发明人： Rajesh B. Khamankar ,  Haowen Bu ,  Douglas Tad Grider

    IPC分类号： H01L29/76

    CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.

    摘要翻译： 包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。 第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。 第二PSD层是Si-Ge，并且包括密度为5×1019原子/ cm3至2×1020原子/ cm3的碳和密度高于5×1019原子/ cm3的硼。 第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。 在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。 一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

    Antimony ion implantation for semiconductor components
    4.
    发明申请
    Antimony ion implantation for semiconductor components 有权
    半导体元件的锑离子注入

    公开(公告)号：US20070218662A1

    公开(公告)日：2007-09-20

    申请号：US11725927

    申请日：2007-03-20

    申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

    发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

    IPC分类号： H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

    摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

    摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

    Drive current improvement from recessed SiGe incorporation close to gate
    6.
    发明授权
    Drive current improvement from recessed SiGe incorporation close to gate 有权
    驱动目前从嵌入式SiGe并入门口的改进

    公开(公告)号：US07244654B2

    公开(公告)日：2007-07-17

    申请号：US10901568

    申请日：2004-07-29

    申请人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    发明人： Pr Chidambaram ,  Douglas T. Grider ,  Brian A. Smith ,  Haowen Bu ,  Lindsey Hall

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

    摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

    摘要翻译： 形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。 然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。 该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。 在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

    High performance CMOS transistors using PMD liner stress
    8.
    发明授权
    High performance CMOS transistors using PMD liner stress 有权
    使用PMD衬垫应力的高性能CMOS晶体管

    公开(公告)号：US07192894B2

    公开(公告)日：2007-03-20

    申请号：US10833419

    申请日：2004-04-28

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L21/31

    CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

    摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

    摘要翻译： 氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

    Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same
    10.
    发明授权
    Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same 有权
    使用湿式蚀刻来制造具有硅化物栅电极的半导体器件的方法以及包括其的集成电路的制造方法

    公开(公告)号：US07157358B2

    公开(公告)日：2007-01-02

    申请号：US10884665

    申请日：2004-07-02

    申请人： Lindsey Hall ,  Haowen Bu ,  Shaofeng Yu

    发明人： Lindsey Hall ,  Haowen Bu ,  Shaofeng Yu

    IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).

    摘要翻译： 本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。 制造半导体器件的方法以及其它可能的步骤，在衬底（210）上形成多晶硅栅电极（250）并在多晶硅栅电极（250）上形成保护层（260），以提供封盖的多晶硅栅电极 （230）。 该方法还包括在邻近多晶硅栅极（250）的表面上形成保护氧化物（510），并且使用湿蚀刻去除保护氧化物（510），湿法蚀刻不会对保护层（260 ）。